140 lines
5.8 KiB
Diff
140 lines
5.8 KiB
Diff
From 90774538ff7755dcc12d997d52b76a484b8c68d2 Mon Sep 17 00:00:00 2001
|
|
From: Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
|
|
Date: Wed, 17 Nov 2021 19:02:54 +0000
|
|
Subject: [PATCH 01/10] aarch64: [SME] Add +sme option to -march
|
|
|
|
Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=57f02370a1e55bf09d3ede5ba6b2fcc78b40200a
|
|
|
|
This series of patches (tagged [SME]) add support for the Scalable
|
|
Matrix Extension. Patch introduces new command line options: +sme, +sme-f64 and
|
|
+sme-i64 to -march command line options.
|
|
|
|
gas/ChangeLog:
|
|
|
|
* NEWS: Updated docs.
|
|
* config/tc-aarch64.c: New SME command line options.
|
|
* doc/c-aarch64.texi: Update docs.
|
|
|
|
include/ChangeLog:
|
|
|
|
* opcode/aarch64.h (AARCH64_FEATURE_SME): New flag.
|
|
(AARCH64_FEATURE_SME_F64): New flag.
|
|
(AARCH64_FEATURE_SME_I64): New flag.
|
|
|
|
opcodes/ChangeLog:
|
|
|
|
* aarch64-tbl.h (SME): New feature object.
|
|
---
|
|
gas/NEWS | 2 ++
|
|
gas/config/tc-aarch64.c | 11 +++++++++++
|
|
gas/doc/c-aarch64.texi | 6 ++++++
|
|
include/opcode/aarch64.h | 3 +++
|
|
opcodes/aarch64-tbl.h | 11 +++++++++++
|
|
5 files changed, 33 insertions(+)
|
|
|
|
diff --git a/gas/NEWS b/gas/NEWS
|
|
index 9e24e4dd..0c5db3bf 100644
|
|
--- a/gas/NEWS
|
|
+++ b/gas/NEWS
|
|
@@ -2,6 +2,8 @@
|
|
|
|
* Add support for Intel AVX512_FP16 instructions.
|
|
|
|
+* Add support for Scalable Matrix Extension (SME) for AArch64.
|
|
+
|
|
Changes in 2.37:
|
|
|
|
* arm-symbianelf support removed.
|
|
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
|
|
index 2eaad63a..f750fad4 100644
|
|
--- a/gas/config/tc-aarch64.c
|
|
+++ b/gas/config/tc-aarch64.c
|
|
@@ -9273,6 +9273,17 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
|
|
| AARCH64_FEATURE_SHA3, 0)},
|
|
{"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM, 0),
|
|
AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0)},
|
|
+ {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME, 0),
|
|
+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2
|
|
+ | AARCH64_FEATURE_BFLOAT16, 0)},
|
|
+ {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64, 0),
|
|
+ AARCH64_FEATURE (AARCH64_FEATURE_SME
|
|
+ | AARCH64_FEATURE_SVE2
|
|
+ | AARCH64_FEATURE_BFLOAT16, 0)},
|
|
+ {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I64, 0),
|
|
+ AARCH64_FEATURE (AARCH64_FEATURE_SME
|
|
+ | AARCH64_FEATURE_SVE2
|
|
+ | AARCH64_FEATURE_BFLOAT16, 0)},
|
|
{"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0),
|
|
AARCH64_ARCH_NONE},
|
|
{"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM, 0),
|
|
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
|
|
index 79dce2f7..1bd93821 100644
|
|
--- a/gas/doc/c-aarch64.texi
|
|
+++ b/gas/doc/c-aarch64.texi
|
|
@@ -210,6 +210,12 @@ automatically cause those extensions to be disabled.
|
|
@tab Enable the Execution and Data and Prediction instructions.
|
|
@item @code{rng} @tab ARMv8.5-A @tab No
|
|
@tab Enable ARMv8.5-A random number instructions.
|
|
+@item @code{sme} @tab Armv9-A @tab No
|
|
+ @tab Enable SME Extension.
|
|
+@item @code{sme-f64} @tab Armv9-A @tab No
|
|
+ @tab Enable SME F64 Extension.
|
|
+@item @code{sme-i64} @tab Armv9-A @tab No
|
|
+ @tab Enable SME I64 Extension.
|
|
@item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
|
|
@tab Enable Speculative Store Bypassing Safe state read and write.
|
|
@item @code{memtag} @tab ARMv8.5-A @tab No
|
|
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
|
|
index 2bbd593c..7256028d 100644
|
|
--- a/include/opcode/aarch64.h
|
|
+++ b/include/opcode/aarch64.h
|
|
@@ -51,6 +51,7 @@ typedef uint32_t aarch64_insn;
|
|
#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */
|
|
#define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */
|
|
#define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */
|
|
+#define AARCH64_FEATURE_SME (1ULL << 14) /* Scalable Matrix Extension. */
|
|
#define AARCH64_FEATURE_LS64 (1ULL << 15) /* Atomic 64-byte load/store. */
|
|
#define AARCH64_FEATURE_PAC (1ULL << 16) /* v8.3 Pointer Authentication. */
|
|
#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */
|
|
@@ -90,6 +91,8 @@ typedef uint32_t aarch64_insn;
|
|
#define AARCH64_FEATURE_F32MM (1ULL << 53)
|
|
#define AARCH64_FEATURE_F64MM (1ULL << 54)
|
|
#define AARCH64_FEATURE_FLAGM (1ULL << 55) /* v8.4 Flag Manipulation. */
|
|
+#define AARCH64_FEATURE_SME_F64 (1ULL << 57) /* SME F64. */
|
|
+#define AARCH64_FEATURE_SME_I64 (1ULL << 58) /* SME I64. */
|
|
|
|
/* Crypto instructions are the combination of AES and SHA2. */
|
|
#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
|
|
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
|
|
index 17ea851c..d63b0810 100644
|
|
--- a/opcodes/aarch64-tbl.h
|
|
+++ b/opcodes/aarch64-tbl.h
|
|
@@ -2401,6 +2401,14 @@ static const aarch64_feature_set aarch64_feature_sve2sm4 =
|
|
AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SM4, 0);
|
|
static const aarch64_feature_set aarch64_feature_sve2bitperm =
|
|
AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_BITPERM, 0);
|
|
+static const aarch64_feature_set aarch64_feature_sme =
|
|
+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME, 0);
|
|
+static const aarch64_feature_set aarch64_feature_sme_f64 =
|
|
+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME
|
|
+ | AARCH64_FEATURE_SME_F64, 0);
|
|
+static const aarch64_feature_set aarch64_feature_sme_i64 =
|
|
+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME
|
|
+ | AARCH64_FEATURE_SME_I64, 0);
|
|
static const aarch64_feature_set aarch64_feature_v8_6 =
|
|
AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0);
|
|
static const aarch64_feature_set aarch64_feature_v8_7 =
|
|
@@ -2458,6 +2466,9 @@ static const aarch64_feature_set aarch64_feature_flagm =
|
|
#define SVE2_SHA3 &aarch64_feature_sve2sha3
|
|
#define SVE2_SM4 &aarch64_feature_sve2sm4
|
|
#define SVE2_BITPERM &aarch64_feature_sve2bitperm
|
|
+#define SME &aarch64_feature_sme
|
|
+#define SME_F64 &aarch64_feature_sme_f64
|
|
+#define SME_I64 &aarch64_feature_sme_i64
|
|
#define ARMV8_6 &aarch64_feature_v8_6
|
|
#define ARMV8_6_SVE &aarch64_feature_v8_6
|
|
#define BFLOAT16_SVE &aarch64_feature_bfloat16_sve
|
|
--
|
|
2.19.1
|
|
|