154 lines
5.4 KiB
Diff
154 lines
5.4 KiB
Diff
From dd79dd44a7e7ebc7533cfdb60f94fe2a4657ce27 Mon Sep 17 00:00:00 2001
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From: Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
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Date: Wed, 17 Nov 2021 20:20:50 +0000
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Subject: [PATCH 07/10] aarch64: [SME] Add new SME system registers
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Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8f1bfdb44894423680a6d56a0994dafb4b82efca
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This patch is adding miscellaneous SME related system registers.
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gas/ChangeLog:
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* testsuite/gas/aarch64/sme-sysreg.d: New test.
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* testsuite/gas/aarch64/sme-sysreg.s: New test.
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* testsuite/gas/aarch64/sme-sysreg-illegal.d: New test.
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* testsuite/gas/aarch64/sme-sysreg-illegal.l: New test.
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* testsuite/gas/aarch64/sme-sysreg-illegal.s: New test.
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opcodes/ChangeLog:
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* aarch64-opc.c: New system registers id_aa64smfr0_el1,
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smcr_el1, smcr_el12, smcr_el2, smcr_el3, smpri_el1,
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smprimap_el2, smidr_el1, tpidr2_el0 and mpamsm_el1.
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---
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.../gas/aarch64/sme-sysreg-illegal.d | 3 ++
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.../gas/aarch64/sme-sysreg-illegal.l | 3 ++
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.../gas/aarch64/sme-sysreg-illegal.s | 3 ++
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gas/testsuite/gas/aarch64/sme-sysreg.d | 29 +++++++++++++++++++
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gas/testsuite/gas/aarch64/sme-sysreg.s | 23 +++++++++++++++
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opcodes/aarch64-opc.c | 12 +++++++-
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6 files changed, 72 insertions(+), 1 deletion(-)
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create mode 100644 gas/testsuite/gas/aarch64/sme-sysreg-illegal.d
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create mode 100644 gas/testsuite/gas/aarch64/sme-sysreg-illegal.l
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create mode 100644 gas/testsuite/gas/aarch64/sme-sysreg-illegal.s
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create mode 100644 gas/testsuite/gas/aarch64/sme-sysreg.d
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create mode 100644 gas/testsuite/gas/aarch64/sme-sysreg.s
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diff --git a/gas/testsuite/gas/aarch64/sme-sysreg-illegal.d b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.d
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new file mode 100644
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index 00000000..ff0e855f
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--- /dev/null
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+++ b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.d
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@@ -0,0 +1,3 @@
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+#as: -march=armv8-a+sme
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+#source: sme-sysreg-illegal.s
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+#warning_output: sme-sysreg-illegal.l
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diff --git a/gas/testsuite/gas/aarch64/sme-sysreg-illegal.l b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.l
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new file mode 100644
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index 00000000..6baad135
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--- /dev/null
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+++ b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.l
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@@ -0,0 +1,3 @@
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+[^:]*: Assembler messages:
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+[^:]*:[0-9]+: Warning: specified register cannot be written to at operand 1 -- `msr id_aa64smfr0_el1,x0'
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+[^:]*:[0-9]+: Warning: specified register cannot be written to at operand 1 -- `msr smidr_el1,x0'
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diff --git a/gas/testsuite/gas/aarch64/sme-sysreg-illegal.s b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.s
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new file mode 100644
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index 00000000..057a6bf0
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--- /dev/null
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+++ b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.s
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@@ -0,0 +1,3 @@
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+/* Write to r/o SME system registers. */
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+msr id_aa64smfr0_el1, x0
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+msr smidr_el1, x0
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diff --git a/gas/testsuite/gas/aarch64/sme-sysreg.d b/gas/testsuite/gas/aarch64/sme-sysreg.d
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new file mode 100644
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index 00000000..8eaf73ca
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--- /dev/null
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+++ b/gas/testsuite/gas/aarch64/sme-sysreg.d
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@@ -0,0 +1,29 @@
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+#name: SME extension (system registers)
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+#as: -march=armv8-a+sme
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+#objdump: -dr
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+
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+.*: file format .*
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+
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+Disassembly of section \.text:
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+
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+0+ <.*>:
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+ 0: d53b4240 mrs x0, svcr
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+ 4: d53804a0 mrs x0, id_aa64smfr0_el1
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+ 8: d53812c0 mrs x0, smcr_el1
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+ c: d53d12c0 mrs x0, smcr_el12
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+ 10: d53c12c0 mrs x0, smcr_el2
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+ 14: d53e12c0 mrs x0, smcr_el3
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+ 18: d5381280 mrs x0, smpri_el1
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+ 1c: d53c12a0 mrs x0, smprimap_el2
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+ 20: d53900c0 mrs x0, smidr_el1
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+ 24: d53bd0a0 mrs x0, tpidr2_el0
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+ 28: d538a560 mrs x0, mpamsm_el1
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+ 2c: d51b4240 msr svcr, x0
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+ 30: d51812c0 msr smcr_el1, x0
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+ 34: d51d12c0 msr smcr_el12, x0
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+ 38: d51c12c0 msr smcr_el2, x0
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+ 3c: d51e12c0 msr smcr_el3, x0
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+ 40: d5181280 msr smpri_el1, x0
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+ 44: d51c12a0 msr smprimap_el2, x0
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+ 48: d51bd0a0 msr tpidr2_el0, x0
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+ 4c: d518a560 msr mpamsm_el1, x0
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diff --git a/gas/testsuite/gas/aarch64/sme-sysreg.s b/gas/testsuite/gas/aarch64/sme-sysreg.s
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new file mode 100644
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index 00000000..ce8a2942
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--- /dev/null
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+++ b/gas/testsuite/gas/aarch64/sme-sysreg.s
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@@ -0,0 +1,23 @@
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+/* Read SME system registers. */
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+mrs x0, svcr
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+mrs x0, id_aa64smfr0_el1
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+mrs x0, smcr_el1
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+mrs x0, smcr_el12
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+mrs x0, smcr_el2
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+mrs x0, smcr_el3
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+mrs x0, smpri_el1
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+mrs x0, smprimap_el2
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+mrs x0, smidr_el1
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+mrs x0, tpidr2_el0
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+mrs x0, mpamsm_el1
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+
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+/* Write to SME system registers. */
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+msr svcr, x0
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+msr smcr_el1, x0
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+msr smcr_el12, x0
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+msr smcr_el2, x0
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+msr smcr_el3, x0
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+msr smpri_el1, x0
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+msr smprimap_el2, x0
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+msr tpidr2_el0, x0
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+msr mpamsm_el1, x0
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diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
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index dba8bcba..923ddefe 100644
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--- a/opcodes/aarch64-opc.c
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+++ b/opcodes/aarch64-opc.c
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@@ -4826,7 +4826,17 @@ const aarch64_sys_reg aarch64_sys_regs [] =
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SR_CORE ("gpccr_el3", CPENC (3,6,C2,C1,6), 0),
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SR_CORE ("gptbr_el3", CPENC (3,6,C2,C1,4), 0),
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- SR_SME ("svcr", CPENC (3,3,C4,C2,2), 0),
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+ SR_SME ("svcr", CPENC (3,3,C4,C2,2), 0),
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+ SR_SME ("id_aa64smfr0_el1", CPENC (3,0,C0,C4,5), F_REG_READ),
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+ SR_SME ("smcr_el1", CPENC (3,0,C1,C2,6), 0),
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+ SR_SME ("smcr_el12", CPENC (3,5,C1,C2,6), 0),
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+ SR_SME ("smcr_el2", CPENC (3,4,C1,C2,6), 0),
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+ SR_SME ("smcr_el3", CPENC (3,6,C1,C2,6), 0),
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+ SR_SME ("smpri_el1", CPENC (3,0,C1,C2,4), 0),
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+ SR_SME ("smprimap_el2", CPENC (3,4,C1,C2,5), 0),
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+ SR_SME ("smidr_el1", CPENC (3,1,C0,C0,6), F_REG_READ),
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+ SR_SME ("tpidr2_el0", CPENC (3,3,C13,C0,5), 0),
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+ SR_SME ("mpamsm_el1", CPENC (3,0,C10,C5,3), 0),
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{ 0, CPENC (0,0,0,0,0), 0, 0 }
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};
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--
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2.19.1
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