Update DPDK version from 19.11 to 20.11 and also support hns3 PMD for Kunpeng 920 and Kunpeng 930. Signed-off-by: speech_white <humin29@huawei.com>
212 lines
7.3 KiB
Diff
212 lines
7.3 KiB
Diff
From b9fbefb52b791730d5720946713e6cb187337652 Mon Sep 17 00:00:00 2001
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From: Hongbo Zheng <zhenghongbo3@huawei.com>
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Date: Thu, 4 Mar 2021 15:44:53 +0800
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Subject: [PATCH 057/189] net/hns3: process MAC interrupt
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TNL is the abbreviation of tunnel, which means port
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here. MAC TNL interrupt indicates the MAC status
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report of the network port, which will be generated
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when the MAC status changes.
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This patch enables MAC TNL interrupt reporting, and
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queries and prints the corresponding MAC status when
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the interrupt is received, then clear the MAC interrupt
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status. Because this interrupt uses the same interrupt
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as RAS, the interrupt log is adjusted.
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Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com>
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Signed-off-by: Lijun Ou <oulijun@huawei.com>
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---
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drivers/net/hns3/hns3_cmd.h | 3 +++
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drivers/net/hns3/hns3_ethdev.c | 57 ++++++++++++++++++++++++++++++++++++------
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drivers/net/hns3/hns3_intr.c | 20 +++++++++++++++
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drivers/net/hns3/hns3_intr.h | 4 +++
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4 files changed, 76 insertions(+), 8 deletions(-)
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diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h
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index 6ceb655..094bf7e 100644
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--- a/drivers/net/hns3/hns3_cmd.h
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+++ b/drivers/net/hns3/hns3_cmd.h
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@@ -116,6 +116,9 @@ enum hns3_opcode_type {
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HNS3_OPC_QUERY_LINK_STATUS = 0x0307,
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HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
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HNS3_OPC_CONFIG_SPEED_DUP = 0x0309,
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+ HNS3_OPC_QUERY_MAC_TNL_INT = 0x0310,
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+ HNS3_OPC_MAC_TNL_INT_EN = 0x0311,
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+ HNS3_OPC_CLEAR_MAC_TNL_INT = 0x0312,
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HNS3_OPC_CONFIG_FEC_MODE = 0x031A,
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/* PFC/Pause commands */
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diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c
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index 1d56916..80f91a7 100644
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--- a/drivers/net/hns3/hns3_ethdev.c
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+++ b/drivers/net/hns3/hns3_ethdev.c
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@@ -217,9 +217,6 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
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goto out;
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}
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- if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
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- hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
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- vector0_int_stats, cmdq_src_val, hw_err_src_reg);
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val = vector0_int_stats;
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ret = HNS3_VECTOR0_EVENT_OTHER;
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out:
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@@ -258,6 +255,34 @@ hns3_clear_all_event_cause(struct hns3_hw *hw)
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}
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static void
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+hns3_handle_mac_tnl(struct hns3_hw *hw)
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+{
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+ struct hns3_cmd_desc desc;
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+ uint32_t status;
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+ int ret;
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+
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+ /* query and clear mac tnl interruptions */
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+ hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
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+ ret = hns3_cmd_send(hw, &desc, 1);
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+ if (ret) {
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+ hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
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+ return;
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+ }
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+
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+ status = rte_le_to_cpu_32(desc.data[0]);
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+ if (status) {
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+ hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
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+ hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
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+ false);
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+ desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
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+ ret = hns3_cmd_send(hw, &desc, 1);
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+ if (ret)
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+ hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
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+ ret);
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+ }
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+}
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+
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+static void
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hns3_interrupt_handler(void *param)
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{
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struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
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@@ -265,24 +290,36 @@ hns3_interrupt_handler(void *param)
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struct hns3_hw *hw = &hns->hw;
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enum hns3_evt_cause event_cause;
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uint32_t clearval = 0;
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+ uint32_t vector0_int;
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+ uint32_t ras_int;
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+ uint32_t cmdq_int;
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/* Disable interrupt */
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hns3_pf_disable_irq0(hw);
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event_cause = hns3_check_event_cause(hns, &clearval);
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+ vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
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+ ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
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+ cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
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/* vector 0 interrupt is shared with reset and mailbox source events. */
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if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
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- hns3_warn(hw, "Received err interrupt");
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+ hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
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+ "ras_int_stat:0x%x cmdq_int_stat:0x%x",
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+ vector0_int, ras_int, cmdq_int);
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hns3_handle_msix_error(hns, &hw->reset.request);
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hns3_handle_ras_error(hns, &hw->reset.request);
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+ hns3_handle_mac_tnl(hw);
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hns3_schedule_reset(hns);
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} else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
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- hns3_warn(hw, "Received reset interrupt");
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+ hns3_warn(hw, "received reset interrupt");
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hns3_schedule_reset(hns);
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- } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
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+ } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
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hns3_dev_handle_mbx_msg(hw);
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- else
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- hns3_err(hw, "Received unknown event");
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+ } else {
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+ hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
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+ "ras_int_stat:0x%x cmdq_int_stat:0x%x",
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+ vector0_int, ras_int, cmdq_int);
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+ }
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hns3_clear_event_cause(hw, event_cause, clearval);
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/* Enable interrupt if it is not cause by reset */
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@@ -4639,6 +4676,8 @@ hns3_update_link_status(struct hns3_hw *hw)
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if (state != hw->mac.link_status) {
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hw->mac.link_status = state;
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hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
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+ hns3_config_mac_tnl_int(hw,
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+ state == ETH_LINK_UP ? true : false);
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return true;
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}
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@@ -4957,6 +4996,7 @@ hns3_uninit_pf(struct rte_eth_dev *eth_dev)
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(void)hns3_firmware_compat_config(hw, false);
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hns3_uninit_umv_space(hw);
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hns3_tqp_stats_uninit(hw);
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+ hns3_config_mac_tnl_int(hw, false);
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hns3_pf_disable_irq0(hw);
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rte_intr_disable(&pci_dev->intr_handle);
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hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
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@@ -5282,6 +5322,7 @@ hns3_dev_stop(struct rte_eth_dev *dev)
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rte_spinlock_lock(&hw->lock);
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if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
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hns3_tm_dev_stop_proc(hw);
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+ hns3_config_mac_tnl_int(hw, false);
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hns3_stop_tqps(hw);
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hns3_do_stop(hns);
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hns3_unmap_rx_interrupt(dev);
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diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c
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index 88ce4c6..2563504 100644
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--- a/drivers/net/hns3/hns3_intr.c
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+++ b/drivers/net/hns3/hns3_intr.c
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@@ -1248,6 +1248,26 @@ enable_ssu_err_intr(struct hns3_adapter *hns, bool en)
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return ret;
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}
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+void
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+hns3_config_mac_tnl_int(struct hns3_hw *hw, bool en)
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+{
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+ struct hns3_cmd_desc desc;
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+ int ret;
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+
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+ hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_TNL_INT_EN, false);
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+ if (en)
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+ desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_EN);
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+ else
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+ desc.data[0] = 0;
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+
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+ desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_EN_MASK);
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+
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+ ret = hns3_cmd_send(hw, &desc, 1);
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+ if (ret)
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+ hns3_err(hw, "fail to %s mac tnl intr, ret = %d",
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+ en ? "enable" : "disable", ret);
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+}
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+
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static int
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config_ppu_err_intrs(struct hns3_adapter *hns, uint32_t cmd, bool en)
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{
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diff --git a/drivers/net/hns3/hns3_intr.h b/drivers/net/hns3/hns3_intr.h
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index 19de1aa..c569a9d 100644
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--- a/drivers/net/hns3/hns3_intr.h
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+++ b/drivers/net/hns3/hns3_intr.h
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@@ -22,6 +22,9 @@
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#define HNS3_MAC_COMMON_ERR_INT_EN 0x107FF
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#define HNS3_MAC_COMMON_ERR_INT_EN_MASK 0x107FF
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+#define HNS3_MAC_TNL_INT_EN GENMASK(9, 0)
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+#define HNS3_MAC_TNL_INT_EN_MASK GENMASK(9, 0)
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+#define HNS3_MAC_TNL_INT_CLR GENMASK(9, 0)
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#define HNS3_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000
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#define HNS3_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000
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@@ -99,6 +102,7 @@ struct hns3_hw_error_desc {
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int hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool state);
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void hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels);
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void hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels);
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+void hns3_config_mac_tnl_int(struct hns3_hw *hw, bool en);
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void hns3_intr_unregister(const struct rte_intr_handle *hdl,
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rte_intr_callback_fn cb_fn, void *cb_arg);
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--
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2.7.4
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