3a8995b1ad
Update DPDK version from 19.11 to 20.11 and also support hns3 PMD for Kunpeng 920 and Kunpeng 930. Signed-off-by: speech_white <humin29@huawei.com>
260 lines
8.8 KiB
Diff
260 lines
8.8 KiB
Diff
From 73fce35c11863c8cccc5444f054e5820f303e9bd Mon Sep 17 00:00:00 2001
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From: Chengwen Feng <fengchengwen@huawei.com>
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Date: Fri, 30 Apr 2021 14:28:48 +0800
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Subject: [PATCH 149/189] net/hns3: improve IO path data cache usage
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This patch improves data cache usage by:
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1. Rearrange the rxq frequency accessed fields in the IO path to the
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first 128B.
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2. Rearrange the txq frequency accessed fields in the IO path to the
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first 64B.
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3. Make sure ptype table align cacheline size which is 128B instead of
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min cacheline size which is 64B because the L1/L2 is 64B and L3 is
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128B on Kunpeng ARM platform.
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The performance gains are 1.5% in 64B packet macfwd scenarios.
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Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
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Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
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---
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drivers/net/hns3/hns3_ethdev.h | 4 +-
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drivers/net/hns3/hns3_rxtx.h | 126 ++++++++++++++++++++++++-----------------
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2 files changed, 77 insertions(+), 53 deletions(-)
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diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h
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index 00fedf0..c70950a 100644
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--- a/drivers/net/hns3/hns3_ethdev.h
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+++ b/drivers/net/hns3/hns3_ethdev.h
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@@ -738,7 +738,7 @@ struct hns3_ptype_table {
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* descriptor, it functions only when firmware report the capability of
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* HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it.
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*/
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- uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned;
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+ uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_aligned;
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};
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#define HNS3_FIXED_MAX_TQP_NUM_MODE 0
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@@ -842,7 +842,7 @@ struct hns3_adapter {
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uint64_t dev_caps_mask;
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- struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
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+ struct hns3_ptype_table ptype_tbl __rte_cache_aligned;
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};
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enum {
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diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h
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index 92f01ed..811be96 100644
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--- a/drivers/net/hns3/hns3_rxtx.h
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+++ b/drivers/net/hns3/hns3_rxtx.h
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@@ -289,22 +289,14 @@ struct hns3_rx_bd_errors_stats {
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};
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struct hns3_rx_queue {
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- void *io_base;
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volatile void *io_head_reg;
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- struct hns3_adapter *hns;
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struct hns3_ptype_table *ptype_tbl;
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struct rte_mempool *mb_pool;
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struct hns3_desc *rx_ring;
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- uint64_t rx_ring_phys_addr; /* RX ring DMA address */
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- const struct rte_memzone *mz;
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struct hns3_entry *sw_ring;
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- struct rte_mbuf *pkt_first_seg;
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- struct rte_mbuf *pkt_last_seg;
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- uint16_t queue_id;
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uint16_t port_id;
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uint16_t nb_rx_desc;
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- uint16_t rx_buf_len;
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/*
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* threshold for the number of BDs waited to passed to hardware. If the
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* number exceeds the threshold, driver will pass these BDs to hardware.
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@@ -318,8 +310,6 @@ struct hns3_rx_queue {
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/* 4 if DEV_RX_OFFLOAD_KEEP_CRC offload set, 0 otherwise */
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uint8_t crc_len;
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- bool rx_deferred_start; /* don't start this queue in dev start */
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- bool configured; /* indicate if rx queue has been configured */
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/*
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* Indicate whether ignore the outer VLAN field in the Rx BD reported
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* by the Hardware. Because the outer VLAN is the PVID if the PVID is
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@@ -331,23 +321,45 @@ struct hns3_rx_queue {
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* driver does not need to perform PVID-related operation in Rx. At this
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* point, the pvid_sw_discard_en will be false.
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*/
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- bool pvid_sw_discard_en;
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- bool ptype_en; /* indicate if the ptype field enabled */
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- bool enabled; /* indicate if Rx queue has been enabled */
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+ uint8_t pvid_sw_discard_en:1;
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+ uint8_t ptype_en:1; /* indicate if the ptype field enabled */
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+
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+ uint64_t mbuf_initializer; /* value to init mbufs used with vector rx */
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+ /* offset_table: used for vector, to solve execute re-order problem */
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+ uint8_t offset_table[HNS3_VECTOR_RX_OFFSET_TABLE_LEN + 1];
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+
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+ uint16_t bulk_mbuf_num; /* indicate bulk_mbuf valid nums */
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struct hns3_rx_basic_stats basic_stats;
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+
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+ struct rte_mbuf *pkt_first_seg;
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+ struct rte_mbuf *pkt_last_seg;
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+
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+ struct rte_mbuf *bulk_mbuf[HNS3_BULK_ALLOC_MBUF_NUM];
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+
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/* DFX statistics that driver does not need to discard packets */
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struct hns3_rx_dfx_stats dfx_stats;
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/* Error statistics that driver needs to discard packets */
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struct hns3_rx_bd_errors_stats err_stats;
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- struct rte_mbuf *bulk_mbuf[HNS3_BULK_ALLOC_MBUF_NUM];
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- uint16_t bulk_mbuf_num;
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-
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- /* offset_table: used for vector, to solve execute re-order problem */
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- uint8_t offset_table[HNS3_VECTOR_RX_OFFSET_TABLE_LEN + 1];
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- uint64_t mbuf_initializer; /* value to init mbufs used with vector rx */
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struct rte_mbuf fake_mbuf; /* fake mbuf used with vector rx */
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+
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+
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+ /*
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+ * The following fields are not accessed in the I/O path, so they are
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+ * placed at the end.
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+ */
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+ void *io_base;
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+ struct hns3_adapter *hns;
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+ uint64_t rx_ring_phys_addr; /* RX ring DMA address */
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+ const struct rte_memzone *mz;
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+
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+ uint16_t queue_id;
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+ uint16_t rx_buf_len;
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+
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+ bool configured; /* indicate if rx queue has been configured */
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+ bool rx_deferred_start; /* don't start this queue in dev start */
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+ bool enabled; /* indicate if Rx queue has been enabled */
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};
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struct hns3_tx_basic_stats {
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@@ -407,16 +419,10 @@ struct hns3_tx_dfx_stats {
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};
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struct hns3_tx_queue {
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- void *io_base;
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volatile void *io_tail_reg;
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- struct hns3_adapter *hns;
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struct hns3_desc *tx_ring;
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- uint64_t tx_ring_phys_addr; /* TX ring DMA address */
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- const struct rte_memzone *mz;
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struct hns3_entry *sw_ring;
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- uint16_t queue_id;
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- uint16_t port_id;
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uint16_t nb_tx_desc;
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/*
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* index of next BD whose corresponding rte_mbuf can be released by
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@@ -432,21 +438,12 @@ struct hns3_tx_queue {
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uint16_t tx_free_thresh;
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/*
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- * For better performance in tx datapath, releasing mbuf in batches is
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- * required.
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- * Only checking the VLD bit of the last descriptor in a batch of the
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- * thresh descriptors does not mean that these descriptors are all sent
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- * by hardware successfully. So we need to check that the VLD bits of
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- * all descriptors are cleared. and then free all mbufs in the batch.
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- * - tx_rs_thresh
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- * Number of mbufs released at a time.
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- *
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- * - free
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- * Tx mbuf free array used for preserving temporarily address of mbuf
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- * released back to mempool, when releasing mbuf in batches.
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+ * The minimum length of the packet supported by hardware in the Tx
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+ * direction.
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*/
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- uint16_t tx_rs_thresh;
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- struct rte_mbuf **free;
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+ uint8_t min_tx_pkt_len;
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+
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+ uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
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/*
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* tso mode.
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@@ -464,7 +461,7 @@ struct hns3_tx_queue {
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* checksum of packets that need TSO, so network driver software
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* not need to recalculate it.
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*/
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- uint8_t tso_mode;
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+ uint16_t tso_mode:1;
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/*
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* udp checksum mode.
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* value range:
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@@ -480,16 +477,10 @@ struct hns3_tx_queue {
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* In this mode, HW does not have the preceding problems and can
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* directly calculate the checksum of these UDP packets.
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*/
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- uint8_t udp_cksum_mode;
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- /*
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- * The minimum length of the packet supported by hardware in the Tx
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- * direction.
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- */
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- uint32_t min_tx_pkt_len;
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+ uint16_t udp_cksum_mode:1;
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- uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
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- bool tx_deferred_start; /* don't start this queue in dev start */
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- bool configured; /* indicate if tx queue has been configured */
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+ uint16_t simple_bd_enable:1;
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+ uint16_t tx_push_enable:1; /* check whether the tx push is enabled */
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/*
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* Indicate whether add the vlan_tci of the mbuf to the inner VLAN field
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* of Tx BD. Because the outer VLAN will always be the PVID when the
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@@ -502,11 +493,44 @@ struct hns3_tx_queue {
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* PVID-related operations in Tx. And pvid_sw_shift_en will be false at
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* this point.
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*/
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- bool pvid_sw_shift_en;
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- bool enabled; /* indicate if Tx queue has been enabled */
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+ uint16_t pvid_sw_shift_en:1;
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+
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+ /*
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+ * For better performance in tx datapath, releasing mbuf in batches is
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+ * required.
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+ * Only checking the VLD bit of the last descriptor in a batch of the
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+ * thresh descriptors does not mean that these descriptors are all sent
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+ * by hardware successfully. So we need to check that the VLD bits of
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+ * all descriptors are cleared. and then free all mbufs in the batch.
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+ * - tx_rs_thresh
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+ * Number of mbufs released at a time.
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+ *
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+ * - free
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+ * Tx mbuf free array used for preserving temporarily address of mbuf
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+ * released back to mempool, when releasing mbuf in batches.
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+ */
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+ uint16_t tx_rs_thresh;
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+ struct rte_mbuf **free;
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struct hns3_tx_basic_stats basic_stats;
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struct hns3_tx_dfx_stats dfx_stats;
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+
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+
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+ /*
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+ * The following fields are not accessed in the I/O path, so they are
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+ * placed at the end.
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+ */
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+ void *io_base;
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+ struct hns3_adapter *hns;
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+ uint64_t tx_ring_phys_addr; /* TX ring DMA address */
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+ const struct rte_memzone *mz;
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+
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+ uint16_t port_id;
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+ uint16_t queue_id;
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+
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+ bool configured; /* indicate if tx queue has been configured */
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+ bool tx_deferred_start; /* don't start this queue in dev start */
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+ bool enabled; /* indicate if Tx queue has been enabled */
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};
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#define HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) \
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--
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2.7.4
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