3d43155151
Sync some patchs from upstreaming for hns3 pmd and modifies are as follow: 1. support flow control autoneg for fiber port 2. support simplify hardware checksum offloading 3. support dump media type 4. add Tx Rx descriptor logs 5. fix Rx multiple firmware reset interrupts 6. ethdev: fix one address occupies two entries in MAC addrs (cherry picked from commit 2af7e093f8ec2ca13cf5b3f372c484b500e07aea)
68 lines
2.5 KiB
Diff
68 lines
2.5 KiB
Diff
From 307e0a26dd0c00b0e600e97c975f0e9d71b175a3 Mon Sep 17 00:00:00 2001
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From: Chengwen Feng <fengchengwen@huawei.com>
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Date: Mon, 22 May 2023 21:17:39 +0800
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Subject: net/hns3: fix Rx multiple firmware reset interrupts
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[ upstream commit 312dd216fe75173016a4c5edce60bb1bea988315 ]
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In the firmware (also known as IMP) reset scenario, driver interrupt
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processing and firmware watchdog initialization are asynchronous.
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If the driver interrupt processing is faster than firmware watchdog
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initialization (that is, the driver clears the firmware reset
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interrupt source before the firmware watchdog is initialized), the
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driver will receive multiple firmware reset interrupts.
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In the Kunpeng 920 platform, the above situation does not exist. But
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it does on the newer platforms. So we add 5ms delay before drivers
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clears the IMP reset interrupt source.
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As for the impact of 5ms, the number of PFs managed by a firmware is
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limited. Therefore, even if a DPDK process takes over all the PFs
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which managed by the firmware, the delay is controllable.
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Fixes: ee930d38ffca ("net/hns3: fix timing of clearing interrupt source")
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Cc: stable@dpdk.org
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Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
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Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
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---
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drivers/net/hns3/hns3_ethdev.c | 14 ++++++++++++++
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1 file changed, 14 insertions(+)
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diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c
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index 8a7f6cc7be..c0df8f5d97 100644
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--- a/drivers/net/hns3/hns3_ethdev.c
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+++ b/drivers/net/hns3/hns3_ethdev.c
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@@ -286,6 +286,19 @@ hns3_handle_mac_tnl(struct hns3_hw *hw)
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}
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}
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+static void
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+hns3_delay_before_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
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+{
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+#define IMPRESET_WAIT_MS_TIME 5
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+
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+ if (event_type == HNS3_VECTOR0_EVENT_RST &&
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+ regclr & BIT(HNS3_VECTOR0_IMPRESET_INT_B) &&
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+ hw->revision >= PCI_REVISION_ID_HIP09_A) {
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+ rte_delay_ms(IMPRESET_WAIT_MS_TIME);
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+ hns3_dbg(hw, "wait firmware watchdog initialization completed.");
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+ }
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+}
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+
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static void
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hns3_interrupt_handler(void *param)
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{
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@@ -305,6 +318,7 @@ hns3_interrupt_handler(void *param)
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vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
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ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
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cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
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+ hns3_delay_before_clear_event_cause(hw, event_cause, clearval);
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hns3_clear_event_cause(hw, event_cause, clearval);
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/* vector 0 interrupt is shared with reset and mailbox source events. */
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if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
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--
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2.23.0
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