8f6a9dec60
Sync some patchs from upstreaming about a segment fault for testpmd app and a IMP reset trigger for hns3 pmd. Patchs are as follow: - ethdev: add API to check if queue is valid - app/testpmd: fix segment fault with invalid queue ID - net/hns3: fix IMP reset trigger (cherry picked from commit 06e0b2741afcd87d686d24608ecb3c974ea83f6d)
67 lines
2.0 KiB
Diff
67 lines
2.0 KiB
Diff
From deb9dd8d00b81173425215f82ba9cb3e0db31e5c Mon Sep 17 00:00:00 2001
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From: Huisong Li <lihuisong@huawei.com>
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Date: Tue, 6 Jun 2023 20:10:28 +0800
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Subject: net/hns3: fix IMP reset trigger
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[ upstream commit bc49e0b4132a05cc012f5e2e7934fbec6589861c ]
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Currently, driver sends the command with an unknown opcode to the
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firmware to trigger IMP reset when some hardware error happened.
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This unknown opcode cannot be parsed by the firmware.
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So this patch fixes the way by writing register to do it.
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Fixes: 2790c6464725 ("net/hns3: support device reset")
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Cc: stable@dpdk.org
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Signed-off-by: Huisong Li <lihuisong@huawei.com>
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Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
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---
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drivers/net/hns3/hns3_ethdev.c | 16 ++++------------
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1 file changed, 4 insertions(+), 12 deletions(-)
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diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c
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index 9af08a7748..6c3ae75c4d 100644
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--- a/drivers/net/hns3/hns3_ethdev.c
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+++ b/drivers/net/hns3/hns3_ethdev.c
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@@ -44,6 +44,7 @@
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#define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
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#define HNS3_VECTOR0_IMP_RD_POISON_B 5U
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#define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
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+#define HNS3_VECTOR0_TRIGGER_IMP_RESET_B 7U
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#define HNS3_RESET_WAIT_MS 100
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#define HNS3_RESET_WAIT_CNT 200
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@@ -5575,17 +5576,6 @@ hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
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return hns3_cmd_send(hw, &desc, 1);
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}
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-static int
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-hns3_imp_reset_cmd(struct hns3_hw *hw)
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-{
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- struct hns3_cmd_desc desc;
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-
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- hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
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- desc.data[0] = 0xeedd;
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-
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- return hns3_cmd_send(hw, &desc, 1);
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-}
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-
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static void
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hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
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{
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@@ -5603,7 +5593,9 @@ hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
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switch (reset_level) {
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case HNS3_IMP_RESET:
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- hns3_imp_reset_cmd(hw);
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+ val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
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+ hns3_set_bit(val, HNS3_VECTOR0_TRIGGER_IMP_RESET_B, 1);
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+ hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
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hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
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tv.tv_sec, tv.tv_usec);
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break;
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--
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2.23.0
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