b0dbcead43
Sync some patchs from upstreaming and modifies are as follow: - maintainers: update for hns3 driver - app/testpmd: add command to flush multicast MAC addresses - app/testpmd: fix help string - app/testpmd: fix multicast address pool leak - net/hns3: optimize SVE Rx performance - net/hns3: optimize rearm mbuf for SVE Rx - net/hns3: optimize free mbuf for SVE Tx - net/hns3: fix order in NEON Rx - net/hns3: fix traffic management dump text alignment - net/hns3: fix traffic management thread safety - net/hns3: fix flushing multicast MAC address - net/hns3: fix error code for multicast resource - net/hns3: fix VF default MAC modified when set failed - net/hns3: fix index to look up table in NEON Rx - net/hns3: fix non-zero weight for disabled TC - config/arm: add HiSilicon HIP10 Signed-off-by: Dengdui Huang <huangdengdui@huawei.com>
90 lines
3.1 KiB
Diff
90 lines
3.1 KiB
Diff
From d967db92088afcb06e7b245109ff35288c8cd3fe Mon Sep 17 00:00:00 2001
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From: Huisong Li <lihuisong@huawei.com>
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Date: Tue, 11 Jul 2023 18:24:46 +0800
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Subject: [PATCH 360/366] net/hns3: optimize free mbuf for SVE Tx
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[ upstream commit 01a295b741603b9366366a665402a2667a29fcc3 ]
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Currently, hns3 SVE Tx checks the valid bits of all descriptors
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in a batch and then determines whether to release the corresponding
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mbufs. Actually, once the valid bit of any descriptor in a batch
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isn't cleared, driver does not need to scan the rest of descriptors.
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If we optimize SVE codes algorithm about this function, the performance
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of a single queue for 64B packet is improved by ~2% on txonly forwarding
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mode. And if use C code to scan all descriptors, the performance is
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improved by ~8%.
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So this patch selects C code to optimize this code to improve the SVE
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Tx performance.
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Signed-off-by: Huisong Li <lihuisong@huawei.com>
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Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
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---
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drivers/net/hns3/hns3_rxtx_vec_sve.c | 42 +---------------------------
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1 file changed, 1 insertion(+), 41 deletions(-)
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diff --git a/drivers/net/hns3/hns3_rxtx_vec_sve.c b/drivers/net/hns3/hns3_rxtx_vec_sve.c
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index 6f23ba6..51d4bf3 100644
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--- a/drivers/net/hns3/hns3_rxtx_vec_sve.c
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+++ b/drivers/net/hns3/hns3_rxtx_vec_sve.c
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@@ -337,46 +337,6 @@ hns3_recv_pkts_vec_sve(void *__restrict rx_queue,
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return nb_rx;
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}
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-static inline void
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-hns3_tx_free_buffers_sve(struct hns3_tx_queue *txq)
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-{
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-#define HNS3_SVE_CHECK_DESCS_PER_LOOP 8
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-#define TX_VLD_U8_ZIP_INDEX svindex_u8(0, 4)
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- svbool_t pg32 = svwhilelt_b32(0, HNS3_SVE_CHECK_DESCS_PER_LOOP);
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- svuint32_t vld, vld2;
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- svuint8_t vld_u8;
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- uint64_t vld_all;
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- struct hns3_desc *tx_desc;
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- int i;
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-
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- /*
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- * All mbufs can be released only when the VLD bits of all
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- * descriptors in a batch are cleared.
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- */
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- /* do logical OR operation for all desc's valid field */
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- vld = svdup_n_u32(0);
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- tx_desc = &txq->tx_ring[txq->next_to_clean];
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- for (i = 0; i < txq->tx_rs_thresh; i += HNS3_SVE_CHECK_DESCS_PER_LOOP,
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- tx_desc += HNS3_SVE_CHECK_DESCS_PER_LOOP) {
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- vld2 = svld1_gather_u32offset_u32(pg32, (uint32_t *)tx_desc,
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- svindex_u32(BD_FIELD_VALID_OFFSET, BD_SIZE));
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- vld = svorr_u32_z(pg32, vld, vld2);
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- }
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- /* shift left and then right to get all valid bit */
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- vld = svlsl_n_u32_z(pg32, vld,
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- HNS3_UINT32_BIT - 1 - HNS3_TXD_VLD_B);
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- vld = svreinterpret_u32_s32(svasr_n_s32_z(pg32,
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- svreinterpret_s32_u32(vld), HNS3_UINT32_BIT - 1));
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- /* use tbl to compress 32bit-lane to 8bit-lane */
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- vld_u8 = svtbl_u8(svreinterpret_u8_u32(vld), TX_VLD_U8_ZIP_INDEX);
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- /* dump compressed 64bit to variable */
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- svst1_u64(PG64_64BIT, &vld_all, svreinterpret_u64_u8(vld_u8));
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- if (vld_all > 0)
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- return;
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-
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- hns3_tx_bulk_free_buffers(txq);
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-}
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-
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static inline void
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hns3_tx_fill_hw_ring_sve(struct hns3_tx_queue *txq,
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struct rte_mbuf **pkts,
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@@ -457,7 +417,7 @@ hns3_xmit_fixed_burst_vec_sve(void *__restrict tx_queue,
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uint16_t nb_tx = 0;
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if (txq->tx_bd_ready < txq->tx_free_thresh)
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- hns3_tx_free_buffers_sve(txq);
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+ hns3_tx_free_buffers(txq);
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nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts);
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if (unlikely(nb_pkts == 0)) {
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--
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2.41.0.windows.2
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