b381e82182
sync patches from 22.07 for hns3, dma and testpmd etc. Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> (cherry picked from commit 7beb6a72fff2920a2d993030b0b02822249707fb)
55 lines
1.7 KiB
Diff
55 lines
1.7 KiB
Diff
From 5b84cc2a652f2646d2d4b4cdc1e6b00c13f4d790 Mon Sep 17 00:00:00 2001
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From: Chengwen Feng <fengchengwen@huawei.com>
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Date: Fri, 27 May 2022 11:40:54 +0800
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Subject: [PATCH 104/122] dma/hisilicon: enhance CQ scan robustness
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The CQ (completion queue) descriptors were updated by hardware, and then
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scanned by driver to retrieve hardware completion status.
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This patch enhances robustness by following:
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1. replace while (true) with a finite loop to avoid potential dead loop.
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2. check the csq_head field in CQ descriptor to avoid status array
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overflows.
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Fixes: 2db4f0b82360 ("dma/hisilicon: add data path")
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Cc: stable@dpdk.org
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Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
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---
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drivers/dma/hisilicon/hisi_dmadev.c | 12 +++++++++++-
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1 file changed, 11 insertions(+), 1 deletion(-)
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diff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c
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index f5c3cd914d..fbe09284ed 100644
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--- a/drivers/dma/hisilicon/hisi_dmadev.c
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+++ b/drivers/dma/hisilicon/hisi_dmadev.c
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@@ -634,7 +634,7 @@ hisi_dma_scan_cq(struct hisi_dma_dev *hw)
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uint16_t count = 0;
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uint64_t misc;
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- while (true) {
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+ while (count < hw->cq_depth) {
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cqe = &hw->cqe[cq_head];
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misc = cqe->misc;
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misc = rte_le_to_cpu_64(misc);
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@@ -642,6 +642,16 @@ hisi_dma_scan_cq(struct hisi_dma_dev *hw)
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break;
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csq_head = FIELD_GET(CQE_SQ_HEAD_MASK, misc);
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+ if (unlikely(csq_head > hw->sq_depth_mask)) {
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+ /**
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+ * Defensive programming to prevent overflow of the
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+ * status array indexed by csq_head. Only error logs
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+ * are used for prompting.
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+ */
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+ HISI_DMA_ERR(hw, "invalid csq_head:%u!\n", csq_head);
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+ count = 0;
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+ break;
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+ }
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if (unlikely(misc & CQE_STATUS_MASK))
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hw->status[csq_head] = FIELD_GET(CQE_STATUS_MASK,
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misc);
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--
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2.22.0
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