1c77287214
sync patches ranges from versoin 9 t0 17 from master branch Signed-off-by: speech_white <humin29@huawei.com>
43 lines
1.5 KiB
Diff
43 lines
1.5 KiB
Diff
From cc6216dd998af8500649b7eeb520af2b80abdb90 Mon Sep 17 00:00:00 2001
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From: Huisong Li <lihuisong@huawei.com>
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Date: Sat, 6 Nov 2021 09:42:58 +0800
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Subject: [PATCH 24/33] net/hns3: simplify queue DMA address arithmetic
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The patch obtains the upper 32 bits of the Rx/Tx queue DMA address in one
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step instead of two steps.
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Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations")
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Cc: stable@dpdk.org
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Signed-off-by: Huisong Li <lihuisong@huawei.com>
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Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
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---
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drivers/net/hns3/hns3_rxtx.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c
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index bb1723e29..b63024997 100644
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--- a/drivers/net/hns3/hns3_rxtx.c
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+++ b/drivers/net/hns3/hns3_rxtx.c
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@@ -310,7 +310,7 @@ hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)
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hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);
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hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,
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- (uint32_t)((dma_addr >> 31) >> 1));
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+ (uint32_t)(dma_addr >> 32));
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hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,
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hns3_buf_size2type(rx_buf_len));
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@@ -325,7 +325,7 @@ hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)
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hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);
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hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,
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- (uint32_t)((dma_addr >> 31) >> 1));
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+ (uint32_t)(dma_addr >> 32));
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hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,
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HNS3_CFG_DESC_NUM(txq->nb_tx_desc));
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--
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2.33.0
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