169 lines
5.4 KiB
Diff
169 lines
5.4 KiB
Diff
From fa4e2267ec2408f95f750167b3d542eeca288124 Mon Sep 17 00:00:00 2001
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From: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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Date: Thu, 1 Jun 2023 09:37:06 +0100
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Subject: [PATCH 073/144] aarch64: Add =r,m and =m,r alternatives to 64-bit
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vector move patterns
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Reference: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=12e71b593ea0c64d919df525cd75ea10b7be8a4b
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We can use the X registers to load and store 64-bit vector modes, we just need to add the alternatives
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to the mov patterns. This straightforward patch does that and for the pair variants too.
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For the testcase in the code we now generate the optimal assembly without any superfluous
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GP<->SIMD moves.
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Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
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gcc/ChangeLog:
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* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>):
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Add =r,m and =r,m alternatives.
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(load_pair<DREG:mode><DREG2:mode>): Likewise.
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(vec_store_pair<DREG:mode><DREG2:mode>): Likewise.
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gcc/testsuite/ChangeLog:
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* gcc.target/aarch64/xreg-vec-modes_1.c: New test.
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---
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gcc/config/aarch64/aarch64-simd.md | 40 ++++++++++--------
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.../gcc.target/aarch64/xreg-vec-modes_1.c | 42 +++++++++++++++++++
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2 files changed, 65 insertions(+), 17 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/aarch64/xreg-vec-modes_1.c
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diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
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index 845f0298e..a974b374b 100644
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--- a/gcc/config/aarch64/aarch64-simd.md
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+++ b/gcc/config/aarch64/aarch64-simd.md
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@@ -116,26 +116,28 @@
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(define_insn "*aarch64_simd_mov<VDMOV:mode>"
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[(set (match_operand:VDMOV 0 "nonimmediate_operand"
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- "=w, m, m, w, ?r, ?w, ?r, w, w")
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+ "=w, r, m, m, m, w, ?r, ?w, ?r, w, w")
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(match_operand:VDMOV 1 "general_operand"
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- "m, Dz, w, w, w, r, r, Dn, Dz"))]
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+ "m, m, Dz, w, r, w, w, r, r, Dn, Dz"))]
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"TARGET_FLOAT
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&& (register_operand (operands[0], <MODE>mode)
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|| aarch64_simd_reg_or_zero (operands[1], <MODE>mode))"
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"@
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ldr\t%d0, %1
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+ ldr\t%x0, %1
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str\txzr, %0
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str\t%d1, %0
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+ str\t%x1, %0
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* return TARGET_SIMD ? \"mov\t%0.<Vbtype>, %1.<Vbtype>\" : \"fmov\t%d0, %d1\";
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* return TARGET_SIMD ? \"umov\t%0, %1.d[0]\" : \"fmov\t%x0, %d1\";
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fmov\t%d0, %1
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mov\t%0, %1
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* return aarch64_output_simd_mov_immediate (operands[1], 64);
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fmov\t%d0, xzr"
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- [(set_attr "type" "neon_load1_1reg<q>, store_8, neon_store1_1reg<q>,\
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- neon_logic<q>, neon_to_gp<q>, f_mcr,\
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+ [(set_attr "type" "neon_load1_1reg<q>, load_8, store_8, neon_store1_1reg<q>,\
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+ store_8, neon_logic<q>, neon_to_gp<q>, f_mcr,\
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mov_reg, neon_move<q>, f_mcr")
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- (set_attr "arch" "*,*,*,*,*,*,*,simd,*")]
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+ (set_attr "arch" "*,*,*,*,*,*,*,*,*,simd,*")]
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)
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(define_insn "*aarch64_simd_mov<VQMOV:mode>"
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@@ -177,31 +179,35 @@
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)
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(define_insn "load_pair<DREG:mode><DREG2:mode>"
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- [(set (match_operand:DREG 0 "register_operand" "=w")
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- (match_operand:DREG 1 "aarch64_mem_pair_operand" "Ump"))
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- (set (match_operand:DREG2 2 "register_operand" "=w")
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- (match_operand:DREG2 3 "memory_operand" "m"))]
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+ [(set (match_operand:DREG 0 "register_operand" "=w,r")
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+ (match_operand:DREG 1 "aarch64_mem_pair_operand" "Ump,Ump"))
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+ (set (match_operand:DREG2 2 "register_operand" "=w,r")
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+ (match_operand:DREG2 3 "memory_operand" "m,m"))]
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"TARGET_FLOAT
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&& rtx_equal_p (XEXP (operands[3], 0),
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plus_constant (Pmode,
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XEXP (operands[1], 0),
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GET_MODE_SIZE (<DREG:MODE>mode)))"
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- "ldp\\t%d0, %d2, %z1"
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- [(set_attr "type" "neon_ldp")]
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+ "@
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+ ldp\t%d0, %d2, %z1
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+ ldp\t%x0, %x2, %z1"
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+ [(set_attr "type" "neon_ldp,load_16")]
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)
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(define_insn "vec_store_pair<DREG:mode><DREG2:mode>"
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- [(set (match_operand:DREG 0 "aarch64_mem_pair_operand" "=Ump")
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- (match_operand:DREG 1 "register_operand" "w"))
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- (set (match_operand:DREG2 2 "memory_operand" "=m")
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- (match_operand:DREG2 3 "register_operand" "w"))]
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+ [(set (match_operand:DREG 0 "aarch64_mem_pair_operand" "=Ump,Ump")
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+ (match_operand:DREG 1 "register_operand" "w,r"))
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+ (set (match_operand:DREG2 2 "memory_operand" "=m,m")
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+ (match_operand:DREG2 3 "register_operand" "w,r"))]
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"TARGET_FLOAT
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&& rtx_equal_p (XEXP (operands[2], 0),
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plus_constant (Pmode,
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XEXP (operands[0], 0),
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GET_MODE_SIZE (<DREG:MODE>mode)))"
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- "stp\\t%d1, %d3, %z0"
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- [(set_attr "type" "neon_stp")]
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+ "@
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+ stp\t%d1, %d3, %z0
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+ stp\t%x1, %x3, %z0"
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+ [(set_attr "type" "neon_stp,store_16")]
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)
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(define_insn "load_pair<VQ:mode><VQ2:mode>"
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diff --git a/gcc/testsuite/gcc.target/aarch64/xreg-vec-modes_1.c b/gcc/testsuite/gcc.target/aarch64/xreg-vec-modes_1.c
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new file mode 100644
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index 000000000..fc4dcb1ad
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/aarch64/xreg-vec-modes_1.c
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@@ -0,0 +1,42 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2" } */
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+/* { dg-final { check-function-bodies "**" "" "" } } */
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+
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+typedef unsigned int v2si __attribute__((vector_size (8)));
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+
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+#define force_gp(V1) asm volatile ("" \
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+ : "=r"(V1) \
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+ : "r"(V1) \
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+ : /* No clobbers */);
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+
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+/*
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+** foo:
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+** ldr (x[0-9]+), \[x1\]
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+** str \1, \[x0\]
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+** ret
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+*/
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+
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+void
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+foo (v2si *a, v2si *b)
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+{
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+ v2si tmp = *b;
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+ force_gp (tmp);
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+ *a = tmp;
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+}
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+
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+/*
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+** foo2:
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+** ldp (x[0-9]+), (x[0-9]+), \[x0\]
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+** stp \1, \2, \[x1\]
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+** ret
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+*/
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+void
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+foo2 (v2si *a, v2si *b)
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+{
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+ v2si t1 = *a;
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+ v2si t2 = a[1];
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+ force_gp (t1);
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+ force_gp (t2);
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+ *b = t1;
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+ b[1] = t2;
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+}
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--
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2.19.1
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