168 lines
5.9 KiB
Diff
168 lines
5.9 KiB
Diff
From 07c9e5c918695ac8dae3a1e3f269e93ca01a3a92 Mon Sep 17 00:00:00 2001
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From: Tamar Christina <tamar.christina@arm.com>
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Date: Wed, 18 Oct 2023 09:34:01 +0100
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Subject: [PATCH 074/144] AArch64: Rewrite simd move immediate patterns to new
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syntax
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Reference: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=04227acbe9e6c60d1e314a6b4f2d949c07f30baa
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This rewrites the simd MOV patterns to use the new compact syntax.
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No change in semantics is expected. This will be needed in follow on patches.
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This also merges the splits into the define_insn which will also be needed soon.
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gcc/ChangeLog:
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PR tree-optimization/109154
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* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>):
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Rewrite to new syntax.
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(*aarch64_simd_mov<VQMOV:mode): Rewrite to new syntax and merge in
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splits.
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---
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gcc/config/aarch64/aarch64-simd.md | 116 ++++++++++++-----------------
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1 file changed, 47 insertions(+), 69 deletions(-)
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diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
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index a974b374b..95cdc16f7 100644
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--- a/gcc/config/aarch64/aarch64-simd.md
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+++ b/gcc/config/aarch64/aarch64-simd.md
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@@ -115,54 +115,59 @@
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)
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(define_insn "*aarch64_simd_mov<VDMOV:mode>"
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- [(set (match_operand:VDMOV 0 "nonimmediate_operand"
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- "=w, r, m, m, m, w, ?r, ?w, ?r, w, w")
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- (match_operand:VDMOV 1 "general_operand"
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- "m, m, Dz, w, r, w, w, r, r, Dn, Dz"))]
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+ [(set (match_operand:VDMOV 0 "nonimmediate_operand")
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+ (match_operand:VDMOV 1 "general_operand"))]
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"TARGET_FLOAT
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&& (register_operand (operands[0], <MODE>mode)
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|| aarch64_simd_reg_or_zero (operands[1], <MODE>mode))"
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- "@
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- ldr\t%d0, %1
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- ldr\t%x0, %1
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- str\txzr, %0
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- str\t%d1, %0
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- str\t%x1, %0
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- * return TARGET_SIMD ? \"mov\t%0.<Vbtype>, %1.<Vbtype>\" : \"fmov\t%d0, %d1\";
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- * return TARGET_SIMD ? \"umov\t%0, %1.d[0]\" : \"fmov\t%x0, %d1\";
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- fmov\t%d0, %1
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- mov\t%0, %1
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- * return aarch64_output_simd_mov_immediate (operands[1], 64);
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- fmov\t%d0, xzr"
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- [(set_attr "type" "neon_load1_1reg<q>, load_8, store_8, neon_store1_1reg<q>,\
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- store_8, neon_logic<q>, neon_to_gp<q>, f_mcr,\
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- mov_reg, neon_move<q>, f_mcr")
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- (set_attr "arch" "*,*,*,*,*,*,*,*,*,simd,*")]
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-)
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-
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-(define_insn "*aarch64_simd_mov<VQMOV:mode>"
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- [(set (match_operand:VQMOV 0 "nonimmediate_operand"
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- "=w, Umn, m, w, ?r, ?w, ?r, w, w")
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- (match_operand:VQMOV 1 "general_operand"
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- "m, Dz, w, w, w, r, r, Dn, Dz"))]
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+ {@ [cons: =0, 1; attrs: type, arch]
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+ [w , m ; neon_load1_1reg<q> , * ] ldr\t%d0, %1
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+ [r , m ; load_8 , * ] ldr\t%x0, %1
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+ [m , Dz; store_8 , * ] str\txzr, %0
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+ [m , w ; neon_store1_1reg<q>, * ] str\t%d1, %0
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+ [m , r ; store_8 , * ] str\t%x1, %0
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+ [w , w ; neon_logic<q> , simd] mov\t%0.<Vbtype>, %1.<Vbtype>
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+ [w , w ; neon_logic<q> , * ] fmov\t%d0, %d1
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+ [?r, w ; neon_to_gp<q> , simd] umov\t%0, %1.d[0]
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+ [?r, w ; neon_to_gp<q> , * ] fmov\t%x0, %d1
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+ [?w, r ; f_mcr , * ] fmov\t%d0, %1
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+ [?r, r ; mov_reg , * ] mov\t%0, %1
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+ [w , Dn; neon_move<q> , simd] << aarch64_output_simd_mov_immediate (operands[1], 64);
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+ [w , Dz; f_mcr , * ] fmov\t%d0, xzr
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+ }
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+)
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+
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+(define_insn_and_split "*aarch64_simd_mov<VQMOV:mode>"
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+ [(set (match_operand:VQMOV 0 "nonimmediate_operand")
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+ (match_operand:VQMOV 1 "general_operand"))]
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"TARGET_FLOAT
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&& (register_operand (operands[0], <MODE>mode)
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|| aarch64_simd_reg_or_zero (operands[1], <MODE>mode))"
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- "@
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- ldr\t%q0, %1
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- stp\txzr, xzr, %0
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- str\t%q1, %0
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- mov\t%0.<Vbtype>, %1.<Vbtype>
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- #
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- #
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- #
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- * return aarch64_output_simd_mov_immediate (operands[1], 128);
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- fmov\t%d0, xzr"
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- [(set_attr "type" "neon_load1_1reg<q>, store_16, neon_store1_1reg<q>,\
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- neon_logic<q>, multiple, multiple,\
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- multiple, neon_move<q>, fmov")
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- (set_attr "length" "4,4,4,4,8,8,8,4,4")
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- (set_attr "arch" "*,*,*,simd,*,*,*,simd,*")]
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+ {@ [cons: =0, 1; attrs: type, arch, length]
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+ [w , m ; neon_load1_1reg<q> , * , 4] ldr\t%q0, %1
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+ [Umn, Dz; store_16 , * , 4] stp\txzr, xzr, %0
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+ [m , w ; neon_store1_1reg<q>, * , 4] str\t%q1, %0
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+ [w , w ; neon_logic<q> , simd, 4] mov\t%0.<Vbtype>, %1.<Vbtype>
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+ [?r , w ; multiple , * , 8] #
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+ [?w , r ; multiple , * , 8] #
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+ [?r , r ; multiple , * , 8] #
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+ [w , Dn; neon_move<q> , simd, 4] << aarch64_output_simd_mov_immediate (operands[1], 128);
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+ [w , Dz; fmov , * , 4] fmov\t%d0, xzr
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+ }
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+ "&& reload_completed
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+ && (REG_P (operands[0])
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+ && REG_P (operands[1])
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+ && !(FP_REGNUM_P (REGNO (operands[0]))
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+ && FP_REGNUM_P (REGNO (operands[1]))))"
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+ [(const_int 0)]
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+ {
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+ if (GP_REGNUM_P (REGNO (operands[0]))
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+ && GP_REGNUM_P (REGNO (operands[1])))
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+ aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
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+ else
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+ aarch64_split_simd_move (operands[0], operands[1]);
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+ DONE;
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+ }
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)
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;; When storing lane zero we can use the normal STR and its more permissive
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@@ -238,33 +243,6 @@
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[(set_attr "type" "neon_stp_q")]
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)
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-
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-(define_split
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- [(set (match_operand:VQMOV 0 "register_operand" "")
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- (match_operand:VQMOV 1 "register_operand" ""))]
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- "TARGET_FLOAT
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- && reload_completed
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- && GP_REGNUM_P (REGNO (operands[0]))
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- && GP_REGNUM_P (REGNO (operands[1]))"
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- [(const_int 0)]
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-{
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- aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
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- DONE;
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-})
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-
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-(define_split
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- [(set (match_operand:VQMOV 0 "register_operand" "")
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- (match_operand:VQMOV 1 "register_operand" ""))]
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- "TARGET_FLOAT
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- && reload_completed
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- && ((FP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operands[1])))
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- || (GP_REGNUM_P (REGNO (operands[0])) && FP_REGNUM_P (REGNO (operands[1]))))"
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- [(const_int 0)]
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-{
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- aarch64_split_simd_move (operands[0], operands[1]);
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- DONE;
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-})
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-
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(define_expand "@aarch64_split_simd_mov<mode>"
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[(set (match_operand:VQMOV 0)
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(match_operand:VQMOV 1))]
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--
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2.19.1
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