From 3a48cd1be0915a0fabbfb3a30bd9b67ccd5c65d3 Mon Sep 17 00:00:00 2001 From: Diachkov Ilia WX1215920 Date: Tue, 12 Dec 2023 10:41:12 +0800 Subject: [PATCH 6/6] Implement AES pattern matching --- gcc/Makefile.in | 1 + gcc/common.opt | 4 ++++ gcc/config/aarch64/aarch64.c | 24 +++++++++++++++++++++ gcc/doc/tm.texi | 29 +++++++++++++++++++++++++ gcc/doc/tm.texi.in | 12 +++++++++++ gcc/passes.def | 1 + gcc/target.def | 41 ++++++++++++++++++++++++++++++++++++ gcc/timevar.def | 1 + gcc/tree-pass.h | 1 + 9 files changed, 114 insertions(+) diff --git a/gcc/Makefile.in b/gcc/Makefile.in index 31bf2cde2..75b28722e 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -1288,6 +1288,7 @@ OBJS = \ cgraphunit.o \ cgraphclones.o \ combine.o \ + crypto-accel.o \ combine-stack-adj.o \ compare-elim.o \ context.o \ diff --git a/gcc/common.opt b/gcc/common.opt index 36b016253..eb995f701 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -1069,6 +1069,10 @@ floop-crc Common Report Var(flag_loop_crc) Optimization Do the loop crc conversion. +fcrypto-accel-aes +Common Report Var(flag_crypto_accel_aes) Init(0) Optimization +Perform crypto acceleration AES pattern matching. + fauto-inc-dec Common Report Var(flag_auto_inc_dec) Init(1) Optimization Generate auto-inc/dec instructions. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index ae9e0802b..75efbcb97 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -23894,6 +23894,30 @@ is_aarch64_stp_insn (int icode) return false; } +machine_mode +aarch64_get_v16qi_mode () +{ + return V16QImode; +} + +#undef TARGET_GET_V16QI_MODE +#define TARGET_GET_V16QI_MODE aarch64_get_v16qi_mode + +#undef TARGET_GEN_REV32V16QI +#define TARGET_GEN_REV32V16QI gen_aarch64_rev32v16qi + +#undef TARGET_GEN_AESEV16QI +#define TARGET_GEN_AESEV16QI gen_aarch64_crypto_aesev16qi + +#undef TARGET_GEN_AESDV16QI +#define TARGET_GEN_AESDV16QI gen_aarch64_crypto_aesdv16qi + +#undef TARGET_GEN_AESMCV16QI +#define TARGET_GEN_AESMCV16QI gen_aarch64_crypto_aesmcv16qi + +#undef TARGET_GEN_AESIMCV16QI +#define TARGET_GEN_AESIMCV16QI gen_aarch64_crypto_aesimcv16qi + #undef TARGET_IS_LDP_INSN #define TARGET_IS_LDP_INSN is_aarch64_ldp_insn diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index ac1d665c5..4a998aa76 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -11870,6 +11870,35 @@ object files that are not referenced from @code{main} and uses export lists. @end defmac +@deftypefn {Target Hook} machine_mode TARGET_GET_V16QI_MODE () +This function get the 16 byte elements vector mode if target supports this. +@end deftypefn + +@deftypefn {Target Hook} rtx TARGET_GEN_REV32V16QI (rtx @var{dest}, rtx @var{src}) +This function generate the byte reverse instruction + of 16 byte elements vector if target supports this. +@end deftypefn + +@deftypefn {Target Hook} rtx TARGET_GEN_AESEV16QI (rtx @var{dest}, rtx @var{src1}, rtx @var{src2}) +This function generate the AES encryption instruction + of 16 byte elements vector if target supports this. +@end deftypefn + +@deftypefn {Target Hook} rtx TARGET_GEN_AESDV16QI (rtx @var{dest}, rtx @var{src1}, rtx @var{src2}) +This function generate the AES decryption instruction + of 16 byte elements vector if target supports this. +@end deftypefn + +@deftypefn {Target Hook} rtx TARGET_GEN_AESMCV16QI (rtx @var{dest}, rtx @var{src}) +This function generate the AES mix columns instruction + of 16 byte elements vector if target supports this. +@end deftypefn + +@deftypefn {Target Hook} rtx TARGET_GEN_AESIMCV16QI (rtx @var{dest}, rtx @var{src}) +This function generate the AES inversed mix columns instruction + of 16 byte elements vector if target supports this. +@end deftypefn + @deftypefn {Target Hook} bool TARGET_IS_LDP_INSN (int @var{icode}) Return true if icode is corresponding to any of the LDP instruction types. @end deftypefn diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 0cd70dda4..f7094d8c2 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -8010,6 +8010,18 @@ object files that are not referenced from @code{main} and uses export lists. @end defmac +@hook TARGET_GET_V16QI_MODE + +@hook TARGET_GEN_REV32V16QI + +@hook TARGET_GEN_AESEV16QI + +@hook TARGET_GEN_AESDV16QI + +@hook TARGET_GEN_AESMCV16QI + +@hook TARGET_GEN_AESIMCV16QI + @hook TARGET_IS_LDP_INSN @hook TARGET_IS_STP_INSN diff --git a/gcc/passes.def b/gcc/passes.def index ba13d897c..da5d71646 100644 --- a/gcc/passes.def +++ b/gcc/passes.def @@ -448,6 +448,7 @@ along with GCC; see the file COPYING3. If not see NEXT_PASS (pass_rtl_fwprop_addr); NEXT_PASS (pass_inc_dec); NEXT_PASS (pass_initialize_regs); + NEXT_PASS (pass_crypto_accel); NEXT_PASS (pass_ud_rtl_dce); NEXT_PASS (pass_combine); NEXT_PASS (pass_if_after_combine); diff --git a/gcc/target.def b/gcc/target.def index 48c8a8234..b4dff78ea 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -2727,6 +2727,47 @@ modes and they have different conditional execution capability, such as ARM.", bool, (void), default_have_conditional_execution) +DEFHOOK +(get_v16qi_mode, + "This function get the 16 byte elements vector mode if target supports this.", + machine_mode, (), + NULL) + +DEFHOOK +(gen_rev32v16qi, + "This function generate the byte reverse instruction\n\ + of 16 byte elements vector if target supports this.", + rtx, (rtx dest, rtx src), + NULL) + +DEFHOOK +(gen_aesev16qi, + "This function generate the AES encryption instruction\n\ + of 16 byte elements vector if target supports this.", + rtx, (rtx dest, rtx src1, rtx src2), + NULL) + +DEFHOOK +(gen_aesdv16qi, + "This function generate the AES decryption instruction\n\ + of 16 byte elements vector if target supports this.", + rtx, (rtx dest, rtx src1, rtx src2), + NULL) + +DEFHOOK +(gen_aesmcv16qi, + "This function generate the AES mix columns instruction\n\ + of 16 byte elements vector if target supports this.", + rtx, (rtx dest, rtx src), + NULL) + +DEFHOOK +(gen_aesimcv16qi, + "This function generate the AES inversed mix columns instruction\n\ + of 16 byte elements vector if target supports this.", + rtx, (rtx dest, rtx src), + NULL) + DEFHOOK (is_ldp_insn, "Return true if icode is corresponding to any of the LDP instruction types.", diff --git a/gcc/timevar.def b/gcc/timevar.def index 24caf1b5d..9ca74dffe 100644 --- a/gcc/timevar.def +++ b/gcc/timevar.def @@ -258,6 +258,7 @@ DEFTIMEVAR (TV_AUTO_INC_DEC , "auto inc dec") DEFTIMEVAR (TV_CSE2 , "CSE 2") DEFTIMEVAR (TV_BRANCH_PROB , "branch prediction") DEFTIMEVAR (TV_COMBINE , "combiner") +DEFTIMEVAR (TV_CRYPTO_ACCEL , "crypto accel") DEFTIMEVAR (TV_IFCVT , "if-conversion") DEFTIMEVAR (TV_MODE_SWITCH , "mode switching") DEFTIMEVAR (TV_SMS , "sms modulo scheduling") diff --git a/gcc/tree-pass.h b/gcc/tree-pass.h index 232a3fdf6..29dc7e34b 100644 --- a/gcc/tree-pass.h +++ b/gcc/tree-pass.h @@ -570,6 +570,7 @@ extern rtl_opt_pass *make_pass_cse2 (gcc::context *ctxt); extern rtl_opt_pass *make_pass_df_initialize_opt (gcc::context *ctxt); extern rtl_opt_pass *make_pass_df_initialize_no_opt (gcc::context *ctxt); extern rtl_opt_pass *make_pass_reginfo_init (gcc::context *ctxt); +extern rtl_opt_pass *make_pass_crypto_accel (gcc::context *ctxt); extern rtl_opt_pass *make_pass_inc_dec (gcc::context *ctxt); extern rtl_opt_pass *make_pass_stack_ptr_mod (gcc::context *ctxt); extern rtl_opt_pass *make_pass_initialize_regs (gcc::context *ctxt); -- 2.33.0