136 lines
5.4 KiB
Diff
136 lines
5.4 KiB
Diff
From 4ca466e1bb19587ff954ce5508e355ed5a12383e Mon Sep 17 00:00:00 2001
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From: Liu Zixian <liuzixian4@huawei.com>
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Date: Thu, 10 Nov 2022 19:10:37 +0800
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Subject: [PATCH] Suppot for sw arch
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Based on version 2.9.1 from wuzx <wuzx1226@qq.com>
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Signed-off-by: Liu Zixian <liuzixian4@huawei.com>
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---
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config.guess | 40 ++++++++++++++++++++++++++++++++++++
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config.sub | 1 +
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configure | 1 +
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src/base/basictypes.h | 2 ++
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src/malloc_hook_mmap_linux.h | 3 ++-
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5 files changed, 46 insertions(+), 1 deletion(-)
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diff --git a/config.guess b/config.guess
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index 7f76b62..abf78f4 100755
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--- a/config.guess
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+++ b/config.guess
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@@ -313,6 +313,36 @@ case $UNAME_MACHINE:$UNAME_SYSTEM:$UNAME_RELEASE:$UNAME_VERSION in
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mips:OSF1:*.*)
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GUESS=mips-dec-osf1
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;;
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+ sw_64:OSF1:*:*)
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+ case $UNAME_RELEASE in
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+ *4.0)
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+ UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'`
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+ ;;
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+ *5.*)
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+ UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'`
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+ ;;
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+ esac
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+ # According to Compaq, /usr/sbin/psrinfo has been available on
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+ # OSF/1 and Tru64 systems produced since 1995. I hope that
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+ # covers most systems running today. This code pipes the CPU
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+ # types through head -n 1, so we only detect the type of CPU 0.
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+ SW_64_CPU_TYPE=`/usr/sbin/psrinfo -v | sed -n -e 's/^ The sw_64 \(.*\) processor.*$/\1/p' | head -n 1`
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+ case "$SW_64_CPU_TYPE" in
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+ "SW6A (1621)")
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+ UNAME_MACHINE=sw_64sw6a ;;
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+ "SW6B (3231)")
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+ UNAME_MACHINE=sw_64sw6b ;;
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+ esac
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+ # A Pn.n version is a patched version.
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+ # A Vn.n version is a released version.
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+ # A Tn.n version is a released field test version.
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+ # A Xn.n version is an unreleased experimental baselevel.
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+ # 1.2 uses "1.2" for uname -r.
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+ GUESS="$UNAME_MACHINE"-dec-osf"`echo "$UNAME_RELEASE" | sed -e 's/^[PVTX]//' | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz`"
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+ # Reset EXIT trap before exiting to avoid spurious non-zero exit code.
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+ exitcode=$?
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+ trap '' 0
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+ ;;
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alpha:OSF1:*:*)
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# Reset EXIT trap before exiting to avoid spurious non-zero exit code.
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trap '' 0
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@@ -976,6 +1006,15 @@ EOF
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UNAME_MACHINE=aarch64_be
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GUESS=$UNAME_MACHINE-unknown-linux-$LIBC
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;;
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+ sw_64:Linux:*:*)
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+ case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in
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+ SW6A) UNAME_MACHINE=sw_64sw6a ;;
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+ SW6B) UNAME_MACHINE=sw_64sw6b ;;
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+ esac
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+ objdump --private-headers /bin/sh | grep -q ld.so.1
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+ if test "$?" = 0 ; then LIBC=gnulibc1 ; fi
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+ GUESS="$UNAME_MACHINE"-unknown-linux-"$LIBC"
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+ ;;
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alpha:Linux:*:*)
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case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' /proc/cpuinfo 2>/dev/null` in
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EV5) UNAME_MACHINE=alphaev5 ;;
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@@ -1512,6 +1551,7 @@ EOF
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UNAME_MACHINE=`(uname -p) 2>/dev/null`
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case $UNAME_MACHINE in
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A*) GUESS=alpha-dec-vms ;;
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+ S*) GUESS=sw_64-dec-vms ;;
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I*) GUESS=ia64-dec-vms ;;
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V*) GUESS=vax-dec-vms ;;
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esac ;;
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diff --git a/config.sub b/config.sub
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index dba16e8..ef3f539 100755
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--- a/config.sub
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+++ b/config.sub
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@@ -1185,6 +1185,7 @@ case $cpu-$vendor in
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| alpha | alphaev[4-8] | alphaev56 | alphaev6[78] \
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| alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] \
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| alphapca5[67] | alpha64pca5[67] \
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+ | sw_64 | sw_64sw6a | sw_64sw6b \
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| am33_2.0 \
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| amdgcn \
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| arc | arceb | arc32 | arc64 \
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diff --git a/configure b/configure
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index 4e0684d..2953fe4 100755
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--- a/configure
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+++ b/configure
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@@ -19496,6 +19496,7 @@ printf %s "checking how to access the program counter from a struct ucontext...
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pc_fields="$pc_fields uc_mcontext.sc_ip" # Linux (ia64)
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pc_fields="$pc_fields uc_mcontext.__pc" # Linux (loongarch64)
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pc_fields="$pc_fields uc_mcontext.pc" # Linux (mips)
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+ pc_fields="$pc_fields uc_mcontext.sc_pc" # Linux (sw_64)
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pc_fields="$pc_fields uc_mcontext.uc_regs->gregs[PT_NIP]" # Linux (ppc)
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pc_fields="$pc_fields uc_mcontext.__gregs[REG_PC]" # Linux (riscv64)
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pc_fields="$pc_fields uc_mcontext.psw.addr" # Linux (s390)
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diff --git a/src/base/basictypes.h b/src/base/basictypes.h
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index a8c9e1c..0ceec52 100644
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--- a/src/base/basictypes.h
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+++ b/src/base/basictypes.h
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@@ -378,6 +378,8 @@ class AssignAttributeStartEnd {
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// some ARMs have shorter cache lines (ARM1176JZF-S is 32 bytes for example) but obviously 64-byte aligned implies 32-byte aligned
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# elif (defined(__mips__))
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# define CACHELINE_ALIGNED __attribute__((aligned(128)))
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+# elif (defined(__sw_64__))
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+# define CACHELINE_ALIGNED __attribute__((aligned(128)))
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# elif (defined(__aarch64__))
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# define CACHELINE_ALIGNED __attribute__((aligned(64)))
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// implementation specific, Cortex-A53 and 57 should have 64 bytes
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diff --git a/src/malloc_hook_mmap_linux.h b/src/malloc_hook_mmap_linux.h
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index c7d8b4b..6de699d 100644
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--- a/src/malloc_hook_mmap_linux.h
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+++ b/src/malloc_hook_mmap_linux.h
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@@ -56,7 +56,8 @@
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|| defined(__aarch64__) \
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|| defined(__loongarch64) \
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|| (defined(_MIPS_SIM) && (_MIPS_SIM == _ABI64 || _MIPS_SIM == _ABIN32)) \
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- || defined(__s390__) || (defined(__riscv) && __riscv_xlen == 64)
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+ || defined(__s390__) || (defined(__riscv) && __riscv_xlen == 64) \
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+ || defined(__sw_64__)
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static inline void* do_mmap64(void *start, size_t length,
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int prot, int flags,
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--
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2.36.1
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