26 lines
2.1 KiB
Diff
26 lines
2.1 KiB
Diff
diff --git a/gst/gstconfig.h.in b/gst/gstconfig.h.in
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index 72b25bb..6c511e2 100644
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--- a/gst/gstconfig.h.in
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+++ b/gst/gstconfig.h.in
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@@ -124,7 +124,7 @@
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* http://docs.oracle.com/cd/E19205-01/820-4155/c++_faq.html#Vers6
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* https://software.intel.com/en-us/node/583402
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*/
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-#if defined(__alpha__) || defined(__arc__) || defined(__arm__) || defined(__aarch64__) || defined(__bfin) || defined(__hppa__) || defined(__nios2__) || defined(__MICROBLAZE__) || defined(__mips__) || defined(__or1k__) || defined(__sh__) || defined(__SH4__) || defined(__sparc__) || defined(__sparc) || defined(__ia64__) || defined(_M_ALPHA) || defined(_M_ARM) || defined(_M_ARM64) || defined(_M_IA64) || defined(__xtensa__) || defined(__e2k__) || defined(__riscv) || defined(__loongarch64) || defined(__ARC64__)
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+#if defined(__alpha__) || defined(__sw_64__) || defined(__arc__) || defined(__arm__) || defined(__aarch64__) || defined(__bfin) || defined(__hppa__) || defined(__nios2__) || defined(__MICROBLAZE__) || defined(__mips__) || defined(__or1k__) || defined(__sh__) || defined(__SH4__) || defined(__sparc__) || defined(__sparc) || defined(__ia64__) || defined(_M_ALPHA) || defined(_M_ARM) || defined(_M_ARM64) || defined(_M_IA64) || defined(__xtensa__) || defined(__e2k__) || defined(__riscv) || defined(__loongarch64) || defined(__ARC64__)
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# define GST_HAVE_UNALIGNED_ACCESS 0
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#elif defined(__i386__) || defined(__i386) || defined(__amd64__) || defined(__amd64) || defined(__x86_64__) || defined(__ppc__) || defined(__ppc64__) || defined(__powerpc__) || defined(__powerpc64__) || defined(__m68k__) || defined(_M_IX86) || defined(_M_AMD64) || defined(_M_X64) || defined(__s390__) || defined(__s390x__) || defined(__zarch__)
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# define GST_HAVE_UNALIGNED_ACCESS 1
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diff --git a/meson.build b/meson.build
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index 65d26c2..3f55a88 100644
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--- a/meson.build
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+++ b/meson.build
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@@ -171,6 +171,7 @@ host_defines = [
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[ 'powerpc', 'HAVE_CPU_PPC' ],
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[ 'powerpc64', 'HAVE_CPU_PPC64' ],
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[ 'alpha', 'HAVE_CPU_ALPHA' ],
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+ [ 'sw_64', 'HAVE_CPU_SW_64' ],
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[ 'sparc', 'HAVE_CPU_SPARC' ],
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[ 'ia64', 'HAVE_CPU_IA64' ],
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[ 'hppa', 'HAVE_CPU_HPPA' ],
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