From befc663ba761c1b334b50de138e57e2a00be4f32 Mon Sep 17 00:00:00 2001
From: veega2022 <zhuweijia@huawei.com>
Date: Wed, 10 May 2023 17:54:59 +0800
Subject: [PATCH 02/18] fix pcie_info cmd print display problem

The spelling of WITDH is incorrect. Change it to WIDTH.

Signed-off-by: hesiyuan <hesiyuan4@huawei.com>
---
 pcie/func_lib/pcie_func/pcie_statistics.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/pcie/func_lib/pcie_func/pcie_statistics.c b/pcie/func_lib/pcie_func/pcie_statistics.c
index f12660d..308a142 100644
--- a/pcie/func_lib/pcie_func/pcie_statistics.c
+++ b/pcie/func_lib/pcie_func/pcie_statistics.c
@@ -22,7 +22,7 @@
 #include "pcie_statistics.h"
 
 static const char *g_global_width_name[GLOBAL_WIDTH_TABLE_SIZE] = {
-	"PCIE_WITDH_X1", "PCIE_WITDH_X2", "PCIE_WITDH_X4", "PCIE_WITDH_X8", "PCIE_WITDH_X16"
+	"PCIE_WIDTH_X1", "PCIE_WIDTH_X2", "PCIE_WIDTH_X4", "PCIE_WIDTH_X8", "PCIE_WIDTH_X16"
 };
 
 static int port_distribution_rsp_data_check(const struct hikp_cmd_ret *cmd_ret, uint32_t *port_num)
@@ -81,7 +81,7 @@ int pcie_port_distribution_get(uint32_t chip_id)
 	for (i = 0; i < pair_num; i++) {
 		if (port_info->info_pair[i].port_width >= HIKP_ARRAY_SIZE(g_global_width_name)) {
 			Info("PCIe Base", "port_id[%u] %s\n", port_info->info_pair[i].port_id,
-			"UNKNOWN_WITDH");
+			"UNKNOWN_WIDTH");
 			continue;
 		}
 		Info("PCIe Base", "port_id[%u] %s\n", port_info->info_pair[i].port_id,
-- 
2.25.1

