79 lines
2.0 KiB
RPMSpec
79 lines
2.0 KiB
RPMSpec
Name: iverilog
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Version: 12.0
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%define uver 12_0
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Release: 2%{?dist}
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Summary: Icarus Verilog is a verilog compiler and simulator
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License: GPLv2
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URL: https://github.com/steveicarus/iverilog
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Source0: https://github.com/steveicarus/iverilog/archive/%{name}-%{uver}.tar.gz
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# [PATCH] Fix compilation with -Werror=format-security
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Patch1: 23e51ef7a8e8e4ba42208936e0a6a25901f58c65.patch
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BuildRequires: autoconf
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BuildRequires: bzip2-devel
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BuildRequires: bison
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BuildRequires: flex
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BuildRequires: gperf
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BuildRequires: gcc-c++
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BuildRequires: readline-devel
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BuildRequires: zlib-devel
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BuildRequires: make
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%description
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Icarus Verilog is a Verilog compiler that generates a variety of
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engineering formats, including simulation. It strives to be true
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to the IEEE-1364 standard.
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%prep
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%autosetup -n %{name}-%{uver}
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# Clean junks from tarball
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find . -type f -name ".git" -exec rm '{}' \;
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rm -rf `find . -type d -name "autom4te.cache" -exec echo '{}' \;`
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%build
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chmod +x autoconf.sh
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sh autoconf.sh
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export CPPFLAGS="$CPPFLAGS -fcommon"
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%configure
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# use make, avoid use V=1 due https://github.com/steveicarus/iverilog/issues/262
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make %{?_smp_mflags}
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%install
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%{__make} prefix=%{buildroot}%{_prefix} \
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bindir=%{buildroot}%{_bindir} \
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libdir=%{buildroot}%{_libdir} \
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libdir64=%{buildroot}%{_libdir} \
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includedir=%{buildroot}%{_includedir} \
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mandir=%{buildroot}%{_mandir} \
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vpidir=%{buildroot}%{_libdir}/ivl/ \
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INSTALL="install -p" \
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install
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%check
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make check
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%files
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%doc BUGS.txt QUICK_START.txt
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%doc ieee1364-notes.txt mingw.txt swift.txt netlist.txt
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%doc t-dll.txt vpi.txt cadpli/cadpli.txt
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%doc xilinx-hint.txt examples/
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%doc va_math.txt tgt-fpga/fpga.txt extensions.txt glossary.txt attributes.txt
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%license COPYING
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%{_bindir}/*
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%{_libdir}/ivl
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%{_mandir}/man1/*
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# headers for PLI: This is intended to be used by the user.
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%{_includedir}/*.h
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# RHBZ 480531
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%{_libdir}/*.a
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%changelog
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* Thu Jun 20 2024 liping <1477412247@qq.com> - 12.0-2
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- Package init
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