42 lines
1.3 KiB
Diff
42 lines
1.3 KiB
Diff
From 41ad98a81cc2c1a85dfdbff16eafe153b99e7866 Mon Sep 17 00:00:00 2001
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From: Tony Luck <tony.luck@intel.com>
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Date: Fri, 3 Dec 2021 09:44:04 -0800
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Subject: [PATCH] mcelog: Change "DDR4" string to "DDR" for i10nm platforms
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There are i10nm platforms that support DDR5 as well as some that support
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DDR4.
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Change the DDR4 string to DDR to avoid confusion.
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Signed-off-by: Tony Luck <tony.luck@intel.com>
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Signed-off-by: Andi Kleen <ak@linux.intel.com>
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---
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i10nm.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/i10nm.c b/i10nm.c
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index b629c27..3a0e97c 100644
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--- a/i10nm.c
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+++ b/i10nm.c
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@@ -191,7 +191,7 @@ static char *imc_1[] = {
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};
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static char *imc_2[] = {
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- [0x00] = "DDR4 command / address parity error",
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+ [0x00] = "DDR command / address parity error",
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[0x20] = "HBM command / address parity error",
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[0x21] = "HBM data parity error",
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};
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@@ -204,7 +204,7 @@ static char *imc_8[] = {
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[0x00] = "DDR-T bad request",
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[0x01] = "DDR Data response to an invalid entry",
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[0x02] = "DDR data response to an entry not expecting data",
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- [0x03] = "DDR4 completion to an invalid entry",
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+ [0x03] = "DDR completion to an invalid entry",
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[0x04] = "DDR-T completion to an invalid entry",
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[0x05] = "DDR data/completion FIFO overflow",
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[0x06] = "DDR-T ERID correctable parity error",
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--
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2.27.0
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