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!44 Add official loongarch64 patches to fix some camera software like cheese crash problem

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From: @suwei1202 
Reviewed-by: @small_leek 
Signed-off-by: @small_leek
This commit is contained in:
openeuler-ci-bot 2024-01-17 12:09:22 +00:00 committed by Gitee
commit 5edf427053
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GPG Key ID: 173E9B9CA92EEF8F
9 changed files with 465 additions and 508 deletions
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482
1000-add-loongarch-support-not-upstream-modified.patch
View File

@ -1,482 +0,0 @@
From b7ce39c71900c356b4161b5ef4d6c8a5ffa12732 Mon Sep 17 00:00:00 2001
From: herengui <herengui@kylinsec.com.cn>
Date: Tue, 29 Aug 2023 11:12:32 +0800
Subject: [PATCH 1000/1001] add loongarch support not upstream modified
Signed-off-by: herengui <herengui@kylinsec.com.cn>
---
meson.build | 14 ++++++
src/gallium/auxiliary/gallivm/lp_bld.h | 4 ++
src/gallium/auxiliary/gallivm/lp_bld_arit.c | 17 ++++++-
src/gallium/auxiliary/gallivm/lp_bld_debug.h | 8 ++++
src/gallium/auxiliary/gallivm/lp_bld_init.c | 34 ++++++++++++--
src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 44 ++++++++++++++++++-
src/gallium/auxiliary/gallivm/lp_bld_misc.h | 3 ++
src/gallium/drivers/llvmpipe/lp_screen.c | 4 +-
src/gallium/drivers/llvmpipe/lp_test_arit.c | 2 +-
src/gallium/include/pipe/p_config.h | 6 +++
src/gallium/targets/dri/meson.build | 1 +
src/gallium/targets/dri/target.c | 1 +
src/loader/pci_id_driver_map.h | 7 +++
src/util/u_cpu_detect.c | 30 +++++++++++++
src/util/u_cpu_detect.h | 2 +
15 files changed, 167 insertions(+), 10 deletions(-)
diff --git a/meson.build b/meson.build
index bd54e78..1a00889 100644
--- a/meson.build
+++ b/meson.build
@@ -176,6 +176,8 @@ if dri_drivers.contains('auto')
dri_drivers = []
elif ['mips', 'mips64', 'riscv32', 'riscv64'].contains(host_machine.cpu_family())
dri_drivers = ['r100', 'r200', 'nouveau']
+ elif ['loongarch64'].contains(host_machine.cpu_family())
+ dri_drivers = []
else
error('Unknown architecture @0@. Please pass -Ddri-drivers to set driver options. Patches gladly accepted to fix this.'.format(
host_machine.cpu_family()))
@@ -215,6 +217,11 @@ if gallium_drivers.contains('auto')
gallium_drivers = [
'r300', 'r600', 'radeonsi', 'nouveau', 'virgl', 'swrast'
]
+ elif ['loongarch64'].contains(host_machine.cpu_family())
+ gallium_drivers = [
+ 'r300', 'r600', 'radeonsi', 'nouveau', 'etnaviv', 'kmsro', 'swrast',
+ 'virgl'
+ ]
else
error('Unknown architecture @0@. Please pass -Dgallium-drivers to set driver options. Patches gladly accepted to fix this.'.format(
host_machine.cpu_family()))
@@ -268,6 +275,8 @@ if _vulkan_drivers.contains('auto')
_vulkan_drivers = ['swrast']
elif ['mips', 'mips64', 'riscv32', 'riscv64'].contains(host_machine.cpu_family())
_vulkan_drivers = ['amd', 'swrast']
+ elif ['loongarch64'].contains(host_machine.cpu_family())
+ _vulkan_drivers = ['amd']
else
error('Unknown architecture @0@. Please pass -Dvulkan-drivers to set driver options. Patches gladly accepted to fix this.'.format(
host_machine.cpu_family()))
@@ -1349,6 +1358,11 @@ elif host_machine.cpu_family() == 'mips64' and host_machine.endian() == 'little'
with_asm_arch = 'mips64el'
pre_args += ['-DUSE_MIPS64EL_ASM']
endif
+elif host_machine.cpu_family() == 'loongarch64'
+ if system_has_kms_drm
+ with_asm_arch = 'loongarch64'
+ pre_args += ['-DUSE_LOONGARCH64_ASM']
+ endif
endif
# Check for standard headers and functions
diff --git a/src/gallium/auxiliary/gallivm/lp_bld.h b/src/gallium/auxiliary/gallivm/lp_bld.h
index 9144428..2fd50dd 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld.h
@@ -82,7 +82,11 @@
#define LLVMCreateBuilder ILLEGAL_LLVM_FUNCTION
#if LLVM_VERSION_MAJOR >= 8
+#if defined(__loongarch__) || defined(__mips__)
+#define GALLIVM_HAVE_CORO 0
+#else
#define GALLIVM_HAVE_CORO 1
+#endif
#else
#define GALLIVM_HAVE_CORO 0
#endif
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_arit.c b/src/gallium/auxiliary/gallivm/lp_bld_arit.c
index 1c71c05..99abcae 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_arit.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_arit.c
@@ -1887,6 +1887,15 @@ arch_rounding_available(const struct lp_type type)
return TRUE;
else if (util_get_cpu_caps()->has_neon)
return TRUE;
+ else if (util_get_cpu_caps()->has_msa &&
+ (type.width * type.length == 128))
+ return ((gallivm_perf & GALLIVM_PERF_USE_ARCH_ROUNDING) ? TRUE : FALSE);
+ else if (util_get_cpu_caps()->has_lsx &&
+ (type.width * type.length == 128))
+ return ((gallivm_perf & GALLIVM_PERF_USE_ARCH_ROUNDING) ? TRUE : FALSE);
+ else if (util_get_cpu_caps()->has_lasx &&
+ (type.width * type.length == 256))
+ return ((gallivm_perf & GALLIVM_PERF_USE_ARCH_ROUNDING) ? TRUE : FALSE);
return FALSE;
}
@@ -1994,7 +2003,8 @@ lp_build_round_arch(struct lp_build_context *bld,
LLVMValueRef a,
enum lp_build_round_mode mode)
{
- if (util_get_cpu_caps()->has_sse4_1 || util_get_cpu_caps()->has_neon) {
+ if (util_get_cpu_caps()->has_sse4_1 || util_get_cpu_caps()->has_neon || util_get_cpu_caps()->has_msa
+ || util_get_cpu_caps()->has_lsx || util_get_cpu_caps()->has_lasx) {
LLVMBuilderRef builder = bld->gallivm->builder;
const struct lp_type type = bld->type;
const char *intrinsic_root;
@@ -2403,7 +2413,10 @@ lp_build_iround(struct lp_build_context *bld,
res = LLVMBuildFAdd(builder, a, half, "");
}
- res = LLVMBuildFPToSI(builder, res, int_vec_type, "");
+ if (type.sign)
+ res = LLVMBuildFPToSI(builder, res, int_vec_type, "");
+ else
+ res = LLVMBuildFPToUI(builder, res, int_vec_type, "");
return res;
}
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.h b/src/gallium/auxiliary/gallivm/lp_bld_debug.h
index a5dd7b8..6c22dc2 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_debug.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_debug.h
@@ -49,6 +49,14 @@
#define GALLIVM_PERF_NO_OPT (1 << 3)
#define GALLIVM_PERF_NO_AOS_SAMPLING (1 << 4)
+#if defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64)
+#define GALLIVM_PERF_OPT_O1 (1 << 5)
+#define GALLIVM_PERF_OPT_O2 (1 << 6)
+#define GALLIVM_PERF_OPT_O3 (1 << 7)
+#endif
+
+#define GALLIVM_PERF_USE_ARCH_ROUNDING (1 << 8)
+
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c
index 3f040ac..64740ec 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c
@@ -46,7 +46,7 @@
#endif
#include <llvm-c/BitWriter.h>
#if GALLIVM_HAVE_CORO
-#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64))
+#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64))
#include <llvm-c/Transforms/IPO.h>
#endif
#include <llvm-c/Transforms/Coroutines.h>
@@ -60,6 +60,12 @@ static const struct debug_named_value lp_bld_perf_flags[] = {
{ "no_quad_lod", GALLIVM_PERF_NO_QUAD_LOD, "disable quad_lod optimization" },
{ "no_aos_sampling", GALLIVM_PERF_NO_AOS_SAMPLING, "disable aos sampling optimization" },
{ "nopt", GALLIVM_PERF_NO_OPT, "disable optimization passes to speed up shader compilation" },
+#if defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64)
+ { "o3", GALLIVM_PERF_OPT_O3, "enable aggressive optimization passes" },
+ { "o2", GALLIVM_PERF_OPT_O2, "enable medium optimization passes" },
+ { "o1", GALLIVM_PERF_OPT_O1, "enable less optimization passes" },
+#endif
+ { "use_arch_rounding", GALLIVM_PERF_USE_ARCH_ROUNDING, "use poor arch rounding function provided by glibc" },
DEBUG_NAMED_VALUE_END
};
@@ -135,7 +141,7 @@ create_pass_manager(struct gallivm_state *gallivm)
}
#if GALLIVM_HAVE_CORO
-#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64))
+#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64))
LLVMAddArgumentPromotionPass(gallivm->cgpassmgr);
LLVMAddFunctionAttrsPass(gallivm->cgpassmgr);
#endif
@@ -267,7 +273,16 @@ init_gallivm_engine(struct gallivm_state *gallivm)
optlevel = None;
}
else {
- optlevel = Default;
+#if defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64)
+ if (gallivm_perf & GALLIVM_PERF_OPT_O3)
+ optlevel = Aggressive;
+ else if (gallivm_perf & GALLIVM_PERF_OPT_O2)
+ optlevel = Default;
+ else if (gallivm_perf & GALLIVM_PERF_OPT_O1)
+ optlevel = Less;
+ else
+#endif
+ optlevel = Default;
}
ret = lp_build_create_jit_compiler_for_module(&gallivm->engine,
@@ -450,7 +465,14 @@ lp_build_init(void)
if (util_get_cpu_caps()->has_avx2 || util_get_cpu_caps()->has_avx) {
lp_native_vector_width = 256;
- } else {
+ } else if (util_get_cpu_caps()->has_lasx) {
+#if defined(PIPE_ARCH_LOONGARCH64)
+ if (lp_probe_lasx())
+ lp_native_vector_width = 256;
+ else
+#endif
+ lp_native_vector_width = 128;
+ } else {
/* Leave it at 128, even when no SIMD extensions are available.
* Really needs to be a multiple of 128 so can fit 4 floats.
*/
@@ -622,6 +644,10 @@ gallivm_compile_module(struct gallivm_state *gallivm)
LLVMAddTargetDependentFunctionAttr(func, "no-frame-pointer-elim-non-leaf", "true");
#endif
+#if defined(PIPE_ARCH_MIPS64)
+ LLVMAddTargetDependentFunctionAttr(func, "target-features", "+nomadd4");
+#endif
+
LLVMRunFunctionPassManager(gallivm->passmgr, func);
func = LLVMGetNextFunction(func);
}
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
index be288ab..675de06 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
@@ -376,7 +376,7 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
llvm::SmallVector<std::string, 16> MAttrs;
-#if LLVM_VERSION_MAJOR >= 4 && (defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64) || defined(PIPE_ARCH_ARM))
+#if LLVM_VERSION_MAJOR >= 4 && (defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64) || defined(PIPE_ARCH_ARM) || defined(PIPE_ARCH_LOONGARCH64))
/* llvm-3.3+ implements sys::getHostCPUFeatures for Arm
* and llvm-3.7+ for x86, which allows us to enable/disable
* code generation based on the results of cpuid on these
@@ -470,6 +470,17 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
MAttrs.push_back("+fp64");
#endif
+#if defined(PIPE_ARCH_MIPS64)
+ /* MSA requires a 64-bit FPU register file */
+ MAttrs.push_back(util_cpu_caps.has_msa ? "+msa" : "-msa");
+ /* Support 64-bit FP registers. */
+ MAttrs.push_back("+fp64");
+ /* General Purpose Registers are 64-bit wide */
+ MAttrs.push_back("+gp64");
+ /* Pointers are 64-bit wide */
+ MAttrs.push_back("+ptr64");
+#endif
+
builder.setMAttrs(MAttrs);
if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
@@ -533,6 +544,13 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
*/
if (MCPU == "generic")
MCPU = util_get_cpu_caps()->has_msa ? "mips64r5" : "mips64r2";
+ else if (MCPU == "loongson3a")
+ MCPU = util_get_cpu_caps()->has_msa ? "mips64r5" : "mips64r2";
+#endif
+
+#if defined(PIPE_ARCH_LOONGARCH64)
+ if (MCPU == "generic")
+ MCPU = "gs464v";
#endif
builder.setMCPU(MCPU);
@@ -573,6 +591,30 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
return 1;
}
+#if defined(PIPE_ARCH_LOONGARCH64)
+extern "C"
+LLVMBool
+lp_probe_lasx(void)
+{
+ using namespace llvm;
+ /* our llvm-8+ implements sys::getHostCPUFeatures for loongarch,
+ * which allows us to enable/disable code generation based
+ * on the results of cpucfg.
+ */
+ llvm::StringMap<bool> features;
+ llvm::sys::getHostCPUFeatures(features);
+
+ for (StringMapIterator<bool> f = features.begin();
+ f != features.end();
+ ++f) {
+
+ if ((*f).first() == "lasx" && (*f).second)
+ return 1;
+ }
+
+ return 0;
+}
+#endif
extern "C"
void
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.h b/src/gallium/auxiliary/gallivm/lp_bld_misc.h
index fa0ce90..f9eb530 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.h
@@ -64,6 +64,9 @@ gallivm_dispose_target_library_info(LLVMTargetLibraryInfoRef library_info);
extern void
lp_set_target_options(void);
+#if defined(PIPE_ARCH_LOONGARCH64)
+extern LLVMBool lp_probe_lasx(void);
+#endif
extern int
lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c
index 839902b..c1ce1cf 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -897,8 +897,8 @@ static void update_cache_sha1_cpu(struct mesa_sha1 *ctx)
* Don't need the cpu cache affinity stuff. The rest
* is contained in first 5 dwords.
*/
- STATIC_ASSERT(offsetof(struct util_cpu_caps_t, num_L3_caches) == 5 * sizeof(uint32_t));
- _mesa_sha1_update(ctx, cpu_caps, 5 * sizeof(uint32_t));
+ STATIC_ASSERT(offsetof(struct util_cpu_caps_t, num_L3_caches) == 6 * sizeof(uint32_t));
+ _mesa_sha1_update(ctx, cpu_caps, 6 * sizeof(uint32_t));
}
static void lp_disk_cache_create(struct llvmpipe_screen *screen)
diff --git a/src/gallium/drivers/llvmpipe/lp_test_arit.c b/src/gallium/drivers/llvmpipe/lp_test_arit.c
index cbea1e2..5d64132 100644
--- a/src/gallium/drivers/llvmpipe/lp_test_arit.c
+++ b/src/gallium/drivers/llvmpipe/lp_test_arit.c
@@ -479,7 +479,7 @@ test_unary(unsigned verbose, FILE *fp, const struct unary_test_t *test, unsigned
continue;
}
- if (!util_get_cpu_caps()->has_neon &&
+ if (!util_get_cpu_caps()->has_neon && !util_get_cpu_caps()->has_msa &&
test->ref == &nearbyintf && length == 2 &&
ref != roundf(testval)) {
/* FIXME: The generic (non SSE) path in lp_build_iround, which is
diff --git a/src/gallium/include/pipe/p_config.h b/src/gallium/include/pipe/p_config.h
index 978aa45..cc55351 100644
--- a/src/gallium/include/pipe/p_config.h
+++ b/src/gallium/include/pipe/p_config.h
@@ -130,6 +130,12 @@
#define PIPE_ARCH_MIPS
#endif
+#if defined(__loongarch64__) || defined(__loongarch64)
+#define PIPE_ARCH_LOONGARCH64
+#elif defined(__loongarch__)
+#define PIPE_ARCH_LOONGARCH
+#endif
+
/*
* Endian detection.
*/
diff --git a/src/gallium/targets/dri/meson.build b/src/gallium/targets/dri/meson.build
index 86f66a6..310d839 100644
--- a/src/gallium/targets/dri/meson.build
+++ b/src/gallium/targets/dri/meson.build
@@ -77,6 +77,7 @@ foreach d : [[with_gallium_kmsro, [
'ingenic-drm_dri.so',
'kirin_dri.so',
'mali-dp_dri.so',
+ 'loongson-drm_dri.so',
'mcde_dri.so',
'mediatek_dri.so',
'meson_dri.so',
diff --git a/src/gallium/targets/dri/target.c b/src/gallium/targets/dri/target.c
index 30c9ee9..aa9f768 100644
--- a/src/gallium/targets/dri/target.c
+++ b/src/gallium/targets/dri/target.c
@@ -106,6 +106,7 @@ DEFINE_LOADER_DRM_ENTRYPOINT(imx_dcss)
DEFINE_LOADER_DRM_ENTRYPOINT(ingenic_drm)
DEFINE_LOADER_DRM_ENTRYPOINT(kirin)
DEFINE_LOADER_DRM_ENTRYPOINT(mali_dp)
+DEFINE_LOADER_DRM_ENTRYPOINT(loongson_drm)
DEFINE_LOADER_DRM_ENTRYPOINT(mcde)
DEFINE_LOADER_DRM_ENTRYPOINT(mediatek)
DEFINE_LOADER_DRM_ENTRYPOINT(meson)
diff --git a/src/loader/pci_id_driver_map.h b/src/loader/pci_id_driver_map.h
index d75b2cc..232e1b7 100644
--- a/src/loader/pci_id_driver_map.h
+++ b/src/loader/pci_id_driver_map.h
@@ -68,6 +68,12 @@ static const int vmwgfx_chip_ids[] = {
#undef CHIPSET
};
+static const int ls7a_chip_ids[] = {
+#define CHIPSET(chip, name, family) chip,
+#include "pci_ids/ls7a1000_pci_ids.h"
+#undef CHIPSET
+};
+
bool is_nouveau_vieux(int fd);
bool is_kernel_i915(int fd);
@@ -90,6 +96,7 @@ static const struct {
{ 0x1002, "radeonsi", NULL, -1 },
{ 0x10de, "nouveau_vieux", NULL, -1, is_nouveau_vieux },
{ 0x10de, "nouveau", NULL, -1, },
+ { 0x0014, "loongson-drm", ls7a_chip_ids, ARRAY_SIZE(ls7a_chip_ids) },
{ 0x1af4, "virtio_gpu", virtio_gpu_chip_ids, ARRAY_SIZE(virtio_gpu_chip_ids) },
{ 0x15ad, "vmwgfx", vmwgfx_chip_ids, ARRAY_SIZE(vmwgfx_chip_ids) },
};
diff --git a/src/util/u_cpu_detect.c b/src/util/u_cpu_detect.c
index 955d087..43675d2 100644
--- a/src/util/u_cpu_detect.c
+++ b/src/util/u_cpu_detect.c
@@ -456,6 +456,30 @@ check_os_mips64_support(void)
}
#endif /* PIPE_ARCH_MIPS64 */
+#if defined(PIPE_ARCH_LOONGARCH64)
+static void
+check_os_loongarch64_support(void)
+{
+#if defined(PIPE_OS_LINUX)
+ Elf64_auxv_t aux;
+ int fd;
+
+ fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC);
+ if (fd >= 0) {
+ while (read(fd, &aux, sizeof(Elf64_auxv_t)) == sizeof(Elf64_auxv_t)) {
+ if (aux.a_type == AT_HWCAP) {
+ uint64_t hwcap = aux.a_un.a_val;
+
+ util_cpu_caps.has_lsx = (hwcap >> 2) & 1;
+ util_cpu_caps.has_lasx = (hwcap >> 3) & 1;
+ break;
+ }
+ }
+ close (fd);
+ }
+#endif /* PIPE_OS_LINUX */
+}
+#endif
static void
get_cpu_topology(void)
@@ -813,6 +837,10 @@ util_cpu_detect_once(void)
check_os_mips64_support();
#endif /* PIPE_ARCH_MIPS64 */
+#if defined(PIPE_ARCH_LOONGARCH64)
+ check_os_loongarch64_support();
+#endif
+
get_cpu_topology();
if (debug_get_option_dump_cpu()) {
@@ -842,6 +870,8 @@ util_cpu_detect_once(void)
printf("util_cpu_caps.has_neon = %u\n", util_cpu_caps.has_neon);
printf("util_cpu_caps.has_msa = %u\n", util_cpu_caps.has_msa);
printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps.has_daz);
+ printf("util_cpu_caps.has_lsx = %u\n", util_cpu_caps.has_lsx);
+ printf("util_cpu_caps.has_lasx = %u\n", util_cpu_caps.has_lasx);
printf("util_cpu_caps.has_avx512f = %u\n", util_cpu_caps.has_avx512f);
printf("util_cpu_caps.has_avx512dq = %u\n", util_cpu_caps.has_avx512dq);
printf("util_cpu_caps.has_avx512ifma = %u\n", util_cpu_caps.has_avx512ifma);
diff --git a/src/util/u_cpu_detect.h b/src/util/u_cpu_detect.h
index 59dd230..cd4319e 100644
--- a/src/util/u_cpu_detect.h
+++ b/src/util/u_cpu_detect.h
@@ -103,6 +103,8 @@ struct util_cpu_caps_t {
unsigned has_daz:1;
unsigned has_neon:1;
unsigned has_msa:1;
+ unsigned has_lsx:1;
+ unsigned has_lasx:1;
unsigned has_avx512f:1;
unsigned has_avx512dq:1;
--
2.41.0

47
1000-meson-add-loongarch64-build-support.patch Normal file
View File

@ -0,0 +1,47 @@
From 4ab7e88994234c14972cde4731e73e5c3bef9502 Mon Sep 17 00:00:00 2001
From: suijingfeng <suijingfeng@loongson.cn>
Date: Sun, 11 Jul 2021 04:23:59 +0800
Subject: [PATCH 1/4] meson: add loongarch64 build support
Signed-off-by: suijingfeng <suijingfeng@loongson.cn>
---
meson.build | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/meson.build b/meson.build
index bd54e78..3242bb7 100644
--- a/meson.build
+++ b/meson.build
@@ -176,6 +176,8 @@ if dri_drivers.contains('auto')
dri_drivers = []
elif ['mips', 'mips64', 'riscv32', 'riscv64'].contains(host_machine.cpu_family())
dri_drivers = ['r100', 'r200', 'nouveau']
+ elif ['loongarch64'].contains(host_machine.cpu_family())
+ dri_drivers = []
else
error('Unknown architecture @0@. Please pass -Ddri-drivers to set driver options. Patches gladly accepted to fix this.'.format(
host_machine.cpu_family()))
@@ -215,6 +217,11 @@ if gallium_drivers.contains('auto')
gallium_drivers = [
'r300', 'r600', 'radeonsi', 'nouveau', 'virgl', 'swrast'
]
+ elif ['loongarch64'].contains(host_machine.cpu_family())
+ gallium_drivers = [
+ 'r300', 'r600', 'radeonsi', 'nouveau', 'etnaviv', 'kmsro', 'swrast',
+ 'virgl'
+ ]
else
error('Unknown architecture @0@. Please pass -Dgallium-drivers to set driver options. Patches gladly accepted to fix this.'.format(
host_machine.cpu_family()))
@@ -268,6 +275,8 @@ if _vulkan_drivers.contains('auto')
_vulkan_drivers = ['swrast']
elif ['mips', 'mips64', 'riscv32', 'riscv64'].contains(host_machine.cpu_family())
_vulkan_drivers = ['amd', 'swrast']
+ elif ['loongarch64'].contains(host_machine.cpu_family())
+ _vulkan_drivers = ['amd', 'swrast']
else
error('Unknown architecture @0@. Please pass -Dvulkan-drivers to set driver options. Patches gladly accepted to fix this.'.format(
host_machine.cpu_family()))
--
2.20.1

23
1001-add-loongarch-support-not-upstream-new.patch
View File

@ -1,23 +0,0 @@
From b28e0132b2ec0e54da1c3d158cbc5578811c5eda Mon Sep 17 00:00:00 2001
From: herengui <herengui@kylinsec.com.cn>
Date: Tue, 29 Aug 2023 11:12:43 +0800
Subject: [PATCH 1001/1001] add loongarch support not upstream new
Signed-off-by: herengui <herengui@kylinsec.com.cn>
---
include/pci_ids/ls7a1000_pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
create mode 100644 include/pci_ids/ls7a1000_pci_ids.h
diff --git a/include/pci_ids/ls7a1000_pci_ids.h b/include/pci_ids/ls7a1000_pci_ids.h
new file mode 100644
index 0000000..96b34aa
--- /dev/null
+++ b/include/pci_ids/ls7a1000_pci_ids.h
@@ -0,0 +1,2 @@
+CHIPSET(0x7A15, GC1000, LOONGSON)
+CHIPSET(0x7A06, DC, LOONGSON)
\ No newline at end of file
--
2.41.0

52
1001-gallivm-temporary-disable-coroutines-on-loongarch64.patch Normal file
View File

@ -0,0 +1,52 @@
From 4605ef15620cb3fea64fc3f1af74722f06937e06 Mon Sep 17 00:00:00 2001
From: suijingfeng <suijingfeng@loongson.cn>
Date: Sun, 11 Jul 2021 06:12:17 +0800
Subject: [PATCH 2/4] gallivm: temporary disable coroutines on loongarch64
Signed-off-by: suijingfeng <suijingfeng@loongson.cn>
---
src/gallium/auxiliary/gallivm/lp_bld.h | 4 ++++
src/gallium/auxiliary/gallivm/lp_bld_init.c | 4 ++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld.h b/src/gallium/auxiliary/gallivm/lp_bld.h
index 9144428..4fdc075 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld.h
@@ -82,7 +82,11 @@
#define LLVMCreateBuilder ILLEGAL_LLVM_FUNCTION
#if LLVM_VERSION_MAJOR >= 8
+#if defined(__loongarch__)
+#define GALLIVM_HAVE_CORO 0
+#else
#define GALLIVM_HAVE_CORO 1
+#endif
#else
#define GALLIVM_HAVE_CORO 0
#endif
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c
index 3f040ac..9c251d8 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c
@@ -46,7 +46,7 @@
#endif
#include <llvm-c/BitWriter.h>
#if GALLIVM_HAVE_CORO
-#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64))
+#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64))
#include <llvm-c/Transforms/IPO.h>
#endif
#include <llvm-c/Transforms/Coroutines.h>
@@ -135,7 +135,7 @@ create_pass_manager(struct gallivm_state *gallivm)
}
#if GALLIVM_HAVE_CORO
-#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64))
+#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64))
LLVMAddArgumentPromotionPass(gallivm->cgpassmgr);
LLVMAddFunctionAttrsPass(gallivm->cgpassmgr);
#endif
--
2.20.1

29
1002-gallivm-arit-use-LLVMBuildFPToUI-when-the-float-is-n.patch Normal file
View File

@ -0,0 +1,29 @@
From 9f3e5b7bbbef4c8fd2f0cbbe62a4fef5582f465f Mon Sep 17 00:00:00 2001
From: suijingfeng <suijingfeng@loongson.cn>
Date: Mon, 16 Aug 2021 14:42:57 +0800
Subject: [PATCH 3/4] gallivm: arit: use LLVMBuildFPToUI when the float is not
signed
---
src/gallium/auxiliary/gallivm/lp_bld_arit.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_arit.c b/src/gallium/auxiliary/gallivm/lp_bld_arit.c
index 1c71c05..b1eb5ef 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_arit.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_arit.c
@@ -2403,7 +2403,10 @@ lp_build_iround(struct lp_build_context *bld,
res = LLVMBuildFAdd(builder, a, half, "");
}
- res = LLVMBuildFPToSI(builder, res, int_vec_type, "");
+ if (type.sign)
+ res = LLVMBuildFPToSI(builder, res, int_vec_type, "");
+ else
+ res = LLVMBuildFPToUI(builder, res, int_vec_type, "");
return res;
}
--
2.20.1

66
1003-gallivm-add-more-optlevel-for-debug-purpose-on-loong.patch Normal file
View File

@ -0,0 +1,66 @@
From 1043c69f60f9042d770bb92627a6f7736637d739 Mon Sep 17 00:00:00 2001
From: suijingfeng <suijingfeng@loongson.cn>
Date: Fri, 9 Jul 2021 15:25:06 +0800
Subject: [PATCH 4/4] gallivm: add more optlevel for debug purpose on
loongarch64
Signed-off-by: suijingfeng <suijingfeng@loongson.cn>
---
src/gallium/auxiliary/gallivm/lp_bld_debug.h | 6 ++++++
src/gallium/auxiliary/gallivm/lp_bld_init.c | 16 ++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.h b/src/gallium/auxiliary/gallivm/lp_bld_debug.h
index a5dd7b8..86604e0 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_debug.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_debug.h
@@ -49,6 +49,12 @@
#define GALLIVM_PERF_NO_OPT (1 << 3)
#define GALLIVM_PERF_NO_AOS_SAMPLING (1 << 4)
+#if defined(PIPE_ARCH_LOONGARCH64)
+#define GALLIVM_PERF_OPT_O1 (1 << 5)
+#define GALLIVM_PERF_OPT_O2 (1 << 6)
+#define GALLIVM_PERF_OPT_O3 (1 << 7)
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c
index 9c251d8..4a9ee17 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c
@@ -60,6 +60,11 @@ static const struct debug_named_value lp_bld_perf_flags[] = {
{ "no_quad_lod", GALLIVM_PERF_NO_QUAD_LOD, "disable quad_lod optimization" },
{ "no_aos_sampling", GALLIVM_PERF_NO_AOS_SAMPLING, "disable aos sampling optimization" },
{ "nopt", GALLIVM_PERF_NO_OPT, "disable optimization passes to speed up shader compilation" },
+#if defined(PIPE_ARCH_LOONGARCH64)
+ { "o3", GALLIVM_PERF_OPT_O3, "enable aggressive optimization passes" },
+ { "o2", GALLIVM_PERF_OPT_O2, "enable medium optimization passes" },
+ { "o1", GALLIVM_PERF_OPT_O1, "enable less optimization passes" },
+#endif
DEBUG_NAMED_VALUE_END
};
@@ -270,6 +275,17 @@ init_gallivm_engine(struct gallivm_state *gallivm)
optlevel = Default;
}
+#if defined(PIPE_ARCH_LOONGARCH64)
+ if (gallivm_perf & GALLIVM_PERF_OPT_O3)
+ optlevel = Aggressive;
+ else if (gallivm_perf & GALLIVM_PERF_OPT_O2)
+ optlevel = Default;
+ else if (gallivm_perf & GALLIVM_PERF_OPT_O1)
+ optlevel = Less;
+ else
+ optlevel = Default;
+#endif
+
ret = lp_build_create_jit_compiler_for_module(&gallivm->engine,
&gallivm->code,
gallivm->cache,
--
2.20.1

208
1004-gallivm-fix-gnome-can-not-start-bug.patch Normal file
View File

@ -0,0 +1,208 @@
From df7eb585789eb03bf9581461edb6fbc93f66aeb7 Mon Sep 17 00:00:00 2001
From: zhaojiale <zhaojiale@loongson.cn>
Date: Fri, 27 Oct 2023 15:34:54 +0800
Subject: [PATCH] gallivm: fix gnome can't start bug
1.Because llvm-12(loongarch) on Euler has some bug, we workaround it in mesa.
We close vector (-lsx) and add float (+d) feature manually.
2.The bl instruction will out of bounds when relocation isn't static.
Setting to static, the bl instruction is replace with multiple instructions.
We workaround it in mesa and set it manually.
Signed-off-by: zhaojiale <zhaojiale@loongson>
---
meson.build | 9 ++++++
.../auxiliary/gallivm/lp_bld_debug.cpp | 6 ++++
src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 13 ++++++++-
src/gallium/auxiliary/gallivm/lp_bld_misc.h | 1 -
src/gallium/drivers/llvmpipe/lp_screen.c | 6 ++--
src/gallium/include/pipe/p_config.h | 6 ++++
src/util/u_cpu_detect.c | 28 +++++++++++++++++++
src/util/u_cpu_detect.h | 2 ++
8 files changed, 66 insertions(+), 5 deletions(-)
diff --git a/meson.build b/meson.build
index 3242bb7..310a7bb 100644
--- a/meson.build
+++ b/meson.build
@@ -1270,6 +1270,15 @@ else
sse41_args = []
endif
+if host_machine.cpu_family().startswith('loongarch64')
+ pre_args += '-DUSE_LSX'
+ with_lsx = true
+ lsx_args = ['-mlsx']
+else
+ with_lsx = false
+ lsx_args = []
+endif
+
# Check for GCC style atomics
dep_atomic = null_dep
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp b/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp
index dda4c7d..c6ce22e 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp
@@ -166,6 +166,12 @@ disassemble(const void* func, std::ostream &buffer)
}
#endif
+#if defined(PIPE_ARCH_LOONGARCH64)
+ if (Size == 4 && (*(uint32_t *)(bytes+pc) >> 26) == 0x13) {
+ break;
+ }
+#endif
+
/*
* Advance.
*/
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
index be288ab..6076057 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
@@ -376,7 +376,7 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
llvm::SmallVector<std::string, 16> MAttrs;
-#if LLVM_VERSION_MAJOR >= 4 && (defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64) || defined(PIPE_ARCH_ARM))
+#if LLVM_VERSION_MAJOR >= 4 && (defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64) || defined(PIPE_ARCH_ARM) || defined(PIPE_ARCH_LOONGARCH64))
/* llvm-3.3+ implements sys::getHostCPUFeatures for Arm
* and llvm-3.7+ for x86, which allows us to enable/disable
* code generation based on the results of cpuid on these
@@ -470,6 +470,12 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
MAttrs.push_back("+fp64");
#endif
+#if defined(PIPE_ARCH_LOONGARCH64)
+ MAttrs.push_back("+d");
+ MAttrs.push_back("-lsx");
+ builder.setRelocationModel(Reloc::Static);
+#endif
+
builder.setMAttrs(MAttrs);
if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
@@ -535,6 +541,11 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
MCPU = util_get_cpu_caps()->has_msa ? "mips64r5" : "mips64r2";
#endif
+#if defined(PIPE_ARCH_LITTLE_ENDIAN) && defined(PIPE_ARCH_LOONGARCH64)
+ if (MCPU == "generic")
+ MCPU = "la464";
+#endif
+
builder.setMCPU(MCPU);
if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
debug_printf("llc -mcpu option: %s\n", MCPU.str().c_str());
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.h b/src/gallium/auxiliary/gallivm/lp_bld_misc.h
index fa0ce90..034f4e2 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.h
@@ -64,7 +64,6 @@ gallivm_dispose_target_library_info(LLVMTargetLibraryInfoRef library_info);
extern void
lp_set_target_options(void);
-
extern int
lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
struct lp_generated_code **OutCode,
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c
index 839902b..ffed792 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -895,10 +895,10 @@ static void update_cache_sha1_cpu(struct mesa_sha1 *ctx)
const struct util_cpu_caps_t *cpu_caps = util_get_cpu_caps();
/*
* Don't need the cpu cache affinity stuff. The rest
- * is contained in first 5 dwords.
+ * is contained in first 6 dwords.
*/
- STATIC_ASSERT(offsetof(struct util_cpu_caps_t, num_L3_caches) == 5 * sizeof(uint32_t));
- _mesa_sha1_update(ctx, cpu_caps, 5 * sizeof(uint32_t));
+ STATIC_ASSERT(offsetof(struct util_cpu_caps_t, num_L3_caches) == 6 * sizeof(uint32_t));
+ _mesa_sha1_update(ctx, cpu_caps, 6 * sizeof(uint32_t));
}
static void lp_disk_cache_create(struct llvmpipe_screen *screen)
diff --git a/src/gallium/include/pipe/p_config.h b/src/gallium/include/pipe/p_config.h
index 978aa45..cc55351 100644
--- a/src/gallium/include/pipe/p_config.h
+++ b/src/gallium/include/pipe/p_config.h
@@ -130,6 +130,12 @@
#define PIPE_ARCH_MIPS
#endif
+#if defined(__loongarch64__) || defined(__loongarch64)
+#define PIPE_ARCH_LOONGARCH64
+#elif defined(__loongarch__)
+#define PIPE_ARCH_LOONGARCH
+#endif
+
/*
* Endian detection.
*/
diff --git a/src/util/u_cpu_detect.c b/src/util/u_cpu_detect.c
index 955d087..f8ce18e 100644
--- a/src/util/u_cpu_detect.c
+++ b/src/util/u_cpu_detect.c
@@ -456,6 +456,30 @@ check_os_mips64_support(void)
}
#endif /* PIPE_ARCH_MIPS64 */
+#if defined(PIPE_ARCH_LOONGARCH64)
+static void
+check_os_loongarch64_support(void)
+{
+#if defined(PIPE_OS_LINUX)
+ Elf64_auxv_t aux;
+ int fd;
+
+ fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC);
+ if (fd >= 0) {
+ while (read(fd, &aux, sizeof(Elf64_auxv_t)) == sizeof(Elf64_auxv_t)) {
+ if (aux.a_type == AT_HWCAP) {
+ uint64_t hwcap = aux.a_un.a_val;
+
+ util_cpu_caps.has_lsx = (hwcap >> 2) & 0;
+ util_cpu_caps.has_lasx = (hwcap >> 3) & 0;
+ break;
+ }
+ }
+ close (fd);
+ }
+#endif /* PIPE_OS_LINUX */
+}
+#endif
static void
get_cpu_topology(void)
@@ -813,6 +837,10 @@ util_cpu_detect_once(void)
check_os_mips64_support();
#endif /* PIPE_ARCH_MIPS64 */
+#if defined(PIPE_ARCH_LOONGARCH64)
+ check_os_loongarch64_support();
+#endif
+
get_cpu_topology();
if (debug_get_option_dump_cpu()) {
diff --git a/src/util/u_cpu_detect.h b/src/util/u_cpu_detect.h
index 59dd230..cd4319e 100644
--- a/src/util/u_cpu_detect.h
+++ b/src/util/u_cpu_detect.h
@@ -103,6 +103,8 @@ struct util_cpu_caps_t {
unsigned has_daz:1;
unsigned has_neon:1;
unsigned has_msa:1;
+ unsigned has_lsx:1;
+ unsigned has_lasx:1;
unsigned has_avx512f:1;
unsigned has_avx512dq:1;
--
2.33.0

53
1005-kmsro-Extend-to-include-loongson-drm-support.patch Normal file
View File

@ -0,0 +1,53 @@
diff -uNr mesa-21.3.1-old/include/pci_ids/ls7a1000_pci_ids.h mesa-21.3.1/include/pci_ids/ls7a1000_pci_ids.h
--- mesa-21.3.1-old/include/pci_ids/ls7a1000_pci_ids.h 1970-01-01 08:00:00.000000000 +0800
+++ mesa-21.3.1/include/pci_ids/ls7a1000_pci_ids.h 2024-01-03 10:23:01.401894312 +0800
@@ -0,0 +1,2 @@
+CHIPSET(0x7A15, GC1000, LOONGSON)
+CHIPSET(0x7A06, DC, LOONGSON)
diff -uNr mesa-21.3.1-old/src/gallium/targets/dri/meson.build mesa-21.3.1/src/gallium/targets/dri/meson.build
--- mesa-21.3.1-old/src/gallium/targets/dri/meson.build 2021-12-02 03:04:14.000000000 +0800
+++ mesa-21.3.1/src/gallium/targets/dri/meson.build 2024-01-03 10:25:16.252537398 +0800
@@ -75,6 +75,7 @@
'imx-drm_dri.so',
'imx-dcss_dri.so',
'ingenic-drm_dri.so',
+ 'loongson-drm_dri.so',
'kirin_dri.so',
'mali-dp_dri.so',
'mcde_dri.so',
diff -uNr mesa-21.3.1-old/src/gallium/targets/dri/target.c mesa-21.3.1/src/gallium/targets/dri/target.c
--- mesa-21.3.1-old/src/gallium/targets/dri/target.c 2021-12-02 03:04:14.000000000 +0800
+++ mesa-21.3.1/src/gallium/targets/dri/target.c 2024-01-03 10:25:56.102318459 +0800
@@ -104,6 +104,7 @@
DEFINE_LOADER_DRM_ENTRYPOINT(imx_drm)
DEFINE_LOADER_DRM_ENTRYPOINT(imx_dcss)
DEFINE_LOADER_DRM_ENTRYPOINT(ingenic_drm)
+DEFINE_LOADER_DRM_ENTRYPOINT(loongson_drm)
DEFINE_LOADER_DRM_ENTRYPOINT(kirin)
DEFINE_LOADER_DRM_ENTRYPOINT(mali_dp)
DEFINE_LOADER_DRM_ENTRYPOINT(mcde)
diff -uNr mesa-21.3.1-old/src/loader/pci_id_driver_map.h mesa-21.3.1/src/loader/pci_id_driver_map.h
--- mesa-21.3.1-old/src/loader/pci_id_driver_map.h 2021-12-02 03:04:14.000000000 +0800
+++ mesa-21.3.1/src/loader/pci_id_driver_map.h 2024-01-03 10:28:54.123807700 +0800
@@ -68,6 +68,13 @@
#undef CHIPSET
};
+static const int ls7a_chip_ids[] = {
+#define CHIPSET(chip, name, family) chip,
+#include "pci_ids/ls7a1000_pci_ids.h"
+#undef CHIPSET
+};
+
+
bool is_nouveau_vieux(int fd);
bool is_kernel_i915(int fd);
@@ -90,6 +97,7 @@
{ 0x1002, "radeonsi", NULL, -1 },
{ 0x10de, "nouveau_vieux", NULL, -1, is_nouveau_vieux },
{ 0x10de, "nouveau", NULL, -1, },
+ { 0x0014, "loongson-drm", ls7a_chip_ids, ARRAY_SIZE(ls7a_chip_ids) },
{ 0x1af4, "virtio_gpu", virtio_gpu_chip_ids, ARRAY_SIZE(virtio_gpu_chip_ids) },
{ 0x15ad, "vmwgfx", vmwgfx_chip_ids, ARRAY_SIZE(vmwgfx_chip_ids) },
};

13
mesa.spec
View File

@ -51,7 +51,7 @@
Name: mesa
Summary: Mesa graphics libraries
Version: 21.3.1
Release: 5
Release: 6
License: MIT
URL: http://www.mesa3d.org
@ -61,8 +61,12 @@ Patch1: backport-fix-build-err-on-arm.patch
Patch2: 0001-evergreen-big-endian.patch
Patch3: add_fangtian_support.patch
Patch1000: 1000-add-loongarch-support-not-upstream-modified.patch
Patch1001: 1001-add-loongarch-support-not-upstream-new.patch
Patch1000: 1000-meson-add-loongarch64-build-support.patch
Patch1001: 1001-gallivm-temporary-disable-coroutines-on-loongarch64.patch
Patch1002: 1002-gallivm-arit-use-LLVMBuildFPToUI-when-the-float-is-n.patch
Patch1003: 1003-gallivm-add-more-optlevel-for-debug-purpose-on-loong.patch
Patch1004: 1004-gallivm-fix-gnome-can-not-start-bug.patch
Patch1005: 1005-kmsro-Extend-to-include-loongson-drm-support.patch
BuildRequires: gcc
BuildRequires: gcc-c++
@ -581,6 +585,9 @@ done
%endif
%changelog
* Mon Jan 8 2024 suwei <suwei@kylinsec.com.cn> - 21.3.1-6
- Add official loongarch64 patches to fix some camera software like cheese crash problem
* Tue Oct 17 2023 yanansong <songyanan5@huawei.com> - 21.3.1-5
- Add fangtian