425 lines
10 KiB
C++
425 lines
10 KiB
C++
/*
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Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; version 2 of the License.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef NDB_INTERPRETER_HPP
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#define NDB_INTERPRETER_HPP
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#include <ndb_types.h>
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#define JAM_FILE_ID 215
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class Interpreter {
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public:
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inline static Uint32 mod4(Uint32 len){
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return len + ((4 - (len & 3)) & 3);
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}
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/**
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* General Mnemonic format
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*
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* i = Instruction - 5 Bits ( 0 - 5 ) max 63
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* x = Register 1 - 3 Bits ( 6 - 8 ) max 7
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* y = Register 2 - 3 Bits ( 9 -11 ) max 7
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* b = Branch offset (only branches)
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*
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* 1111111111222222222233
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* 01234567890123456789012345678901
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* iiiiiixxxyyy bbbbbbbbbbbbbbbb
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*
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*
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*/
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/**
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* Instructions
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*/
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STATIC_CONST( READ_ATTR_INTO_REG = 1 );
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STATIC_CONST( WRITE_ATTR_FROM_REG = 2 );
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STATIC_CONST( LOAD_CONST_NULL = 3 );
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STATIC_CONST( LOAD_CONST16 = 4 );
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STATIC_CONST( LOAD_CONST32 = 5 );
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STATIC_CONST( LOAD_CONST64 = 6 );
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STATIC_CONST( ADD_REG_REG = 7 );
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STATIC_CONST( SUB_REG_REG = 8 );
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STATIC_CONST( BRANCH = 9 );
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STATIC_CONST( BRANCH_REG_EQ_NULL = 10 );
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STATIC_CONST( BRANCH_REG_NE_NULL = 11 );
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STATIC_CONST( BRANCH_EQ_REG_REG = 12 );
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STATIC_CONST( BRANCH_NE_REG_REG = 13 );
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STATIC_CONST( BRANCH_LT_REG_REG = 14 );
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STATIC_CONST( BRANCH_LE_REG_REG = 15 );
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STATIC_CONST( BRANCH_GT_REG_REG = 16 );
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STATIC_CONST( BRANCH_GE_REG_REG = 17 );
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STATIC_CONST( EXIT_OK = 18 );
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STATIC_CONST( EXIT_REFUSE = 19 );
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STATIC_CONST( CALL = 20 );
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STATIC_CONST( RETURN = 21 );
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STATIC_CONST( EXIT_OK_LAST = 22 );
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STATIC_CONST( BRANCH_ATTR_OP_ARG = 23 );
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STATIC_CONST( BRANCH_ATTR_EQ_NULL = 24 );
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STATIC_CONST( BRANCH_ATTR_NE_NULL = 25 );
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STATIC_CONST( BRANCH_ATTR_OP_ARG_2 = 26 );
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/**
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* Macros for creating code
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*/
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static Uint32 Read(Uint32 AttrId, Uint32 Register);
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static Uint32 Write(Uint32 AttrId, Uint32 Register);
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static Uint32 LoadNull(Uint32 Register);
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static Uint32 LoadConst16(Uint32 Register, Uint32 Value);
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static Uint32 LoadConst32(Uint32 Register); // Value in next word
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static Uint32 LoadConst64(Uint32 Register); // Value in next 2 words
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static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
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static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
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static Uint32 Branch(Uint32 Inst, Uint32 Reg1, Uint32 Reg2);
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static Uint32 ExitOK();
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static Uint32 ExitLastOK();
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/**
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* Branch OP_ARG
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*
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* i = Instruction - 5 Bits ( 0 - 5 ) max 63
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* a = Attribute id - 16 bits
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* l = Length of string (bytes) - 16 bits OP_ARG
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* p = parameter no - 16 bits OP_ARG_2
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* b = Branch offset (words) - 16 bits
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* t = branch type - 4 bits
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* d = Array length diff
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* v = Varchar flag
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*
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* 1111111111222222222233
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* 01234567890123456789012345678901
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* iiiiii ddvttttbbbbbbbbbbbbbbbb
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* aaaaaaaaaaaaaaaallllllllllllllll
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* -string.... -
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*/
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enum UnaryCondition {
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IS_NULL = 0,
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IS_NOT_NULL = 1
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};
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enum BinaryCondition {
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EQ = 0,
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NE = 1,
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LT = 2,
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LE = 3,
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GT = 4,
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GE = 5,
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LIKE = 6,
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NOT_LIKE = 7,
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AND_EQ_MASK = 8,
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AND_NE_MASK = 9,
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AND_EQ_ZERO = 10,
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AND_NE_ZERO = 11
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};
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// TODO : Remove other 2 unused parameters.
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static Uint32 BranchCol(BinaryCondition cond,
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Uint32 arrayLengthDiff, Uint32 varchar);
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static Uint32 BranchCol_2(Uint32 AttrId);
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static Uint32 BranchCol_2(Uint32 AttrId, Uint32 Len);
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static Uint32 BranchColParameter(BinaryCondition cond);
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static Uint32 BranchColParameter_2(Uint32 AttrId, Uint32 ParamNo);
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static Uint32 getBinaryCondition(Uint32 op1);
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static Uint32 getArrayLengthDiff(Uint32 op1);
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static Uint32 isVarchar(Uint32 op1);
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static Uint32 getBranchCol_AttrId(Uint32 op2);
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static Uint32 getBranchCol_Len(Uint32 op2);
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static Uint32 getBranchCol_ParamNo(Uint32 op2);
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/**
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* Macros for decoding code
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*/
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static Uint32 getOpCode(Uint32 op);
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static Uint32 getReg1(Uint32 op);
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static Uint32 getReg2(Uint32 op);
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static Uint32 getReg3(Uint32 op);
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static Uint32 getLabel(Uint32 op);
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/**
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* Instruction pre-processing required.
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*/
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enum InstructionPreProcessing
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{
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NONE,
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LABEL_ADDRESS_REPLACEMENT,
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SUB_ADDRESS_REPLACEMENT
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};
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/* This method is used to determine what sort of
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* instruction processing is required, and the address
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* of the next instruction in the stream
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*/
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static Uint32 *getInstructionPreProcessingInfo(Uint32 *op,
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InstructionPreProcessing& processing);
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};
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inline
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Uint32
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Interpreter::Read(Uint32 AttrId, Uint32 Register){
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return (AttrId << 16) + (Register << 6) + READ_ATTR_INTO_REG;
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}
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inline
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Uint32
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Interpreter::Write(Uint32 AttrId, Uint32 Register){
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return (AttrId << 16) + (Register << 6) + WRITE_ATTR_FROM_REG;
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}
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inline
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Uint32
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Interpreter::LoadNull(Uint32 Register){
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return (Register << 6) + LOAD_CONST_NULL;
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}
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inline
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Uint32
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Interpreter::LoadConst16(Uint32 Register, Uint32 Value){
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return (Value << 16) + (Register << 6) + LOAD_CONST16;
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}
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inline
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Uint32
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Interpreter::LoadConst32(Uint32 Register){
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return (Register << 6) + LOAD_CONST32;
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}
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inline
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Uint32
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Interpreter::LoadConst64(Uint32 Register){
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return (Register << 6) + LOAD_CONST64;
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}
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inline
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Uint32
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Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){
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return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG;
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}
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inline
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Uint32
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Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){
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return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG;
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}
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inline
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Uint32
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Interpreter::Branch(Uint32 Inst, Uint32 Reg1, Uint32 Reg2){
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return (Reg1 << 9) + (Reg2 << 6) + Inst;
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}
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inline
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Uint32
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Interpreter::BranchCol(BinaryCondition cond,
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Uint32 arrayLengthDiff,
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Uint32 varchar){
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//ndbout_c("BranchCol: cond=%d diff=%u varchar=%u",
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//cond, arrayLengthDiff, varchar);
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return
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BRANCH_ATTR_OP_ARG +
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(arrayLengthDiff << 9) +
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(varchar << 11) +
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(cond << 12);
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}
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inline
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Uint32
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Interpreter::BranchColParameter(BinaryCondition cond)
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{
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return BRANCH_ATTR_OP_ARG_2 + (cond << 12);
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}
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inline
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Uint32
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Interpreter::BranchColParameter_2(Uint32 AttrId, Uint32 ParamNo){
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return (AttrId << 16) + ParamNo;
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}
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inline
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Uint32
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Interpreter::BranchCol_2(Uint32 AttrId, Uint32 Len){
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return (AttrId << 16) + Len;
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}
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inline
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Uint32
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Interpreter::BranchCol_2(Uint32 AttrId){
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return (AttrId << 16);
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}
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inline
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Uint32
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Interpreter::getBinaryCondition(Uint32 op){
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return (op >> 12) & 0xf;
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}
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inline
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Uint32
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Interpreter::getArrayLengthDiff(Uint32 op){
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return (op >> 9) & 0x3;
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}
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inline
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Uint32
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Interpreter::isVarchar(Uint32 op){
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return (op >> 11) & 1;
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}
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inline
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Uint32
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Interpreter::getBranchCol_AttrId(Uint32 op){
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return (op >> 16) & 0xFFFF;
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}
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inline
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Uint32
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Interpreter::getBranchCol_Len(Uint32 op){
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return op & 0xFFFF;
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}
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inline
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Uint32
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Interpreter::getBranchCol_ParamNo(Uint32 op){
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return op & 0xFFFF;
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}
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inline
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Uint32
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Interpreter::ExitOK(){
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return EXIT_OK;
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}
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inline
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Uint32
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Interpreter::ExitLastOK(){
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return EXIT_OK_LAST;
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}
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inline
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Uint32
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Interpreter::getOpCode(Uint32 op){
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return op & 0x3f;
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}
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inline
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Uint32
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Interpreter::getReg1(Uint32 op){
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return (op >> 6) & 0x7;
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}
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inline
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Uint32
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Interpreter::getReg2(Uint32 op){
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return (op >> 9) & 0x7;
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}
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inline
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Uint32
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Interpreter::getReg3(Uint32 op){
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return (op >> 16) & 0x7;
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}
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inline
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Uint32
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Interpreter::getLabel(Uint32 op){
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return (op >> 16) & 0xffff;
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}
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inline
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Uint32*
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Interpreter::getInstructionPreProcessingInfo(Uint32 *op,
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InstructionPreProcessing& processing )
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{
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/* Given an instruction, get a pointer to the
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* next instruction in the stream.
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* Returns NULL on error.
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*/
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processing= NONE;
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Uint32 opCode= getOpCode(*op);
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switch( opCode )
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{
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case READ_ATTR_INTO_REG:
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case WRITE_ATTR_FROM_REG:
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case LOAD_CONST_NULL:
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case LOAD_CONST16:
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return op + 1;
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case LOAD_CONST32:
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return op + 2;
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case LOAD_CONST64:
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return op + 3;
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case ADD_REG_REG:
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case SUB_REG_REG:
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return op + 1;
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case BRANCH:
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case BRANCH_REG_EQ_NULL:
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case BRANCH_REG_NE_NULL:
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case BRANCH_EQ_REG_REG:
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case BRANCH_NE_REG_REG:
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case BRANCH_LT_REG_REG:
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case BRANCH_LE_REG_REG:
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case BRANCH_GT_REG_REG:
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case BRANCH_GE_REG_REG:
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processing= LABEL_ADDRESS_REPLACEMENT;
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return op + 1;
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case BRANCH_ATTR_OP_ARG:
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{
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/* We need to take the length from the second word of the
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* branch instruction so we can skip over the inline const
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* comparison data.
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*/
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processing= LABEL_ADDRESS_REPLACEMENT;
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Uint32 byteLength= getBranchCol_Len(*(op+1));
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Uint32 wordLength= (byteLength + 3) >> 2;
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return op+2+wordLength;
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}
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case BRANCH_ATTR_OP_ARG_2:
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{
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/* We need to take the length from the second word of the
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* branch instruction so we can skip over the inline const
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* comparison data.
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*/
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processing= LABEL_ADDRESS_REPLACEMENT;
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return op+2;
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}
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case BRANCH_ATTR_EQ_NULL:
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case BRANCH_ATTR_NE_NULL:
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processing= LABEL_ADDRESS_REPLACEMENT;
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return op+2;
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case EXIT_OK:
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case EXIT_OK_LAST:
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case EXIT_REFUSE:
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return op+1;
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case CALL:
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processing= SUB_ADDRESS_REPLACEMENT;
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case RETURN:
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return op+1;
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default:
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return NULL;
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}
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}
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#undef JAM_FILE_ID
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#endif
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