94 lines
3.0 KiB
Diff
94 lines
3.0 KiB
Diff
diff -Nur a/src/configure b/src/configure
|
|
--- a/src/configure 2019-03-05 03:56:23.000000000 +0800
|
|
+++ b/src/configure 2023-02-13 17:08:10.253893840 +0800
|
|
@@ -4628,7 +4628,7 @@
|
|
|
|
# First set pthread-mutexes based on arch
|
|
case $arch in
|
|
- aarch64|arm*|parisc*)
|
|
+ aarch64|arm*|parisc*|riscv*)
|
|
pthread_mutexes=yes
|
|
CFLAGS="$CFLAGS -DUSE_PTHREAD_MUTEXES"
|
|
echo "forcing use of pthread mutexes... " >&6
|
|
diff -Nur a/src/configure.in b/src/configure.in
|
|
--- a/src/configure.in 2019-03-05 03:56:23.000000000 +0800
|
|
+++ b/src/configure.in 2023-02-13 17:08:46.854487430 +0800
|
|
@@ -378,7 +378,7 @@
|
|
|
|
# First set pthread-mutexes based on arch
|
|
case $arch in
|
|
- aarch64|arm*|parisc*)
|
|
+ aarch64|arm*|parisc*|riscv*)
|
|
pthread_mutexes=yes
|
|
CFLAGS="$CFLAGS -DUSE_PTHREAD_MUTEXES"
|
|
echo "forcing use of pthread mutexes... " >&6
|
|
diff -Nur a/src/libpfm4/config.mk b/src/libpfm4/config.mk
|
|
--- a/src/libpfm4/config.mk 2019-03-05 03:56:23.000000000 +0800
|
|
+++ b/src/libpfm4/config.mk 2023-02-13 17:11:16.328911611 +0800
|
|
@@ -177,6 +177,9 @@
|
|
CONFIG_PFMLIB_CELL=y
|
|
endif
|
|
|
|
+ifeq ($(ARCH),riscv64)
|
|
+CONFIG_PFMLIB_ARCH_RISCV64=y
|
|
+endif
|
|
|
|
#
|
|
# you shouldn't have to touch anything beyond this point
|
|
diff -Nur a/src/linux-context.h b/src/linux-context.h
|
|
--- a/src/linux-context.h 2019-03-05 03:56:23.000000000 +0800
|
|
+++ b/src/linux-context.h 2023-02-13 17:11:00.932661914 +0800
|
|
@@ -37,6 +37,8 @@
|
|
#define OVERFLOW_ADDRESS(ctx) ctx.ucontext->uc_mcontext.pc
|
|
#elif defined(__hppa__)
|
|
#define OVERFLOW_ADDRESS(ctx) ctx.ucontext->uc_mcontext.sc_iaoq[0]
|
|
+#elif defined(__riscv)
|
|
+#define OVERFLOW_ADDRESS(ctx) ctx.ucontext->uc_mcontext.__gregs[REG_PC]
|
|
#else
|
|
#error "OVERFLOW_ADDRESS() undefined!"
|
|
#endif
|
|
diff -Nur a/src/linux-timer.c b/src/linux-timer.c
|
|
--- a/src/linux-timer.c 2019-03-05 03:56:23.000000000 +0800
|
|
+++ b/src/linux-timer.c 2023-02-13 17:11:16.332911675 +0800
|
|
@@ -288,6 +288,27 @@
|
|
return 0;
|
|
}
|
|
|
|
+/************************/
|
|
+/* riscv64 get_cycles() */
|
|
+/************************/
|
|
+
|
|
+#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 64
|
|
+static inline long long
|
|
+get_cycles( void )
|
|
+{
|
|
+ register unsigned long ret;
|
|
+
|
|
+ __asm__ __volatile__ ("rdcycle %0" : "=r" (ret));
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+/*
|
|
+ * TODO: riscv32 implementation can be done following example in:
|
|
+ * Volume I: RISC-V User-Level ISA V2.2
|
|
+ * 2.8 Control and Status Register Instructions
|
|
+ * Timers and Counters
|
|
+ */
|
|
|
|
#elif !defined(HAVE_GETTIMEOFDAY) && !defined(HAVE_CLOCK_GETTIME)
|
|
#error "No get_cycles support for this architecture. "
|
|
diff -Nur a/src/mb.h b/src/mb.h
|
|
--- a/src/mb.h 2019-03-05 03:56:23.000000000 +0800
|
|
+++ b/src/mb.h 2023-02-13 17:11:16.332911675 +0800
|
|
@@ -39,6 +39,9 @@
|
|
#elif defined(__aarch64__)
|
|
#define rmb() asm volatile("dmb ld" ::: "memory")
|
|
|
|
+#elif defined(__riscv)
|
|
+#define rmb() asm volatile("fence ir, ir" ::: "memory")
|
|
+
|
|
#elif defined(__mips__)
|
|
#define rmb() asm volatile( \
|
|
".set mips2\n\t" \
|