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3 Commits

Author SHA1 Message Date
Chen Qun
7896616008 target/arm: only set ID_PFR1_EL1.GIC for AArch32 guest 
Some AArch64 CPU doesn't support AArch32 mode, and the values of AArch32
registers are all 0.  Hence, We'd better not to modify AArch32 registers
in AArch64 mode.

Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com>
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
Signed-off-by: Dongxu Sun <sundongxu3@huawei.com>
 2022-02-11 21:01:24 +08:00
liuxiangdong
701a2b0a08 Package init 2022-01-29 09:56:33 +08:00
imxcc
d609107256 some bugfix sync from 20.09 
Signed-off-by: imxcc <xingchaochao@huawei.com>
 2021-07-28 15:19:15 +08:00