qemu/target-i386-Introduce-Icelake-Server-v7-to-enable-TS.patch
Jiabo Feng 90057151bb QEMU update to version 6.2.0-92:
- s390x/sclp: Simplify get_sclp_device()
- target/ppc: Remove msr_pr macro
- docs/system/target-arm: Re-alphabetize board list
- migration: Extend query-migrate to provide dirty page limit info
- migration: Implement dirty-limit convergence algo
- migration: Put the detection logic before auto-converge checking
- migration: Refactor auto-converge capability logic
- migration: Introduce dirty-limit capability
- qapi/migration: Introduce vcpu-dirty-limit parameters
- qapi/migration: Introduce x-vcpu-dirty-limit-period parameter
- Change the value of no_ged from true to false
- Allow UNIX socket option for VNC websocket
- tpm_emulator: Avoid double initialization during
- chardev/char-socket: Update AF_UNIX for Windows
- KVM: dirty ring: add missing memory barrier
- i386: reset KVM nested state upon CPU reset
- esp: Handle CMD_BUSRESET by resetting the SCSI bus
- dbus-vmstate: Restrict error checks to registered proxies in dbus_get_proxies
- vfio/pci: Add Ascend310b scend910b support
- target/i386: Export RFDS bit to guests
- target/i386: Add new CPU model SierraForest
- target/i386: Introduce Icelake-Server-v7 to enable TSX
- hw/virtio: handle un-configured shutdown in virtio-pci
- target/s390x: display deprecation status in '-cpu  help'
- target/i386: display deprecation status in '-cpu  help'
- pc-bios/s390-ccw: Fix booting with logical block size < physical block size

Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com>
2024-06-13 14:32:49 +08:00

65 lines
2.4 KiB
Diff

From 2f722c0308c72223e1fe13caf1a3e5843635c98e Mon Sep 17 00:00:00 2001
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: Wed, 20 Mar 2024 17:31:38 +0800
Subject: [PATCH] target/i386: Introduce Icelake-Server-v7 to enable TSX
commit c895fa54e3060c5ac6f3888dce96c9b78626072b upstream.
When start L2 guest with both L1/L2 using Icelake-Server-v3 or above,
QEMU reports below warning:
"warning: host doesn't support requested feature: MSR(10AH).taa-no [bit 8]"
Reason is QEMU Icelake-Server-v3 has TSX feature disabled but enables taa-no
bit. It's meaningless that TSX isn't supported but still claim TSX is secure.
So L1 KVM doesn't expose taa-no to L2 if TSX is unsupported, then starting L2
triggers the warning.
Fix it by introducing a new version Icelake-Server-v7 which has both TSX
and taa-no features. Then guest can use TSX securely when it see taa-no.
This matches the production Icelake which supports TSX and isn't susceptible
to TSX Async Abort (TAA) vulnerabilities, a.k.a, taa-no.
Ideally, TSX should have being enabled together with taa-no since v3, but for
compatibility, we'd better to add v7 to enable it.
Fixes: d965dc35592d ("target/i386: Add ARCH_CAPABILITIES related bits into Icelake-Server CPU model")
Intel-SIG: commit c895fa54e306 target/i386: Introduce Icelake-Server-v7 to enable TSX.
6.2.0-Add SRF CPU module support
Tested-by: Xiangfei Ma <xiangfeix.ma@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Message-ID: <20240320093138.80267-2-zhenzhong.duan@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
[ Quanxian Wang: amend commit log ]
Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
---
target/i386/cpu.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 62ac5ed005..b5bf5ce7aa 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3606,6 +3606,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
},
},
+ {
+ .version = 7,
+ .note = "TSX, taa-no",
+ .props = (PropValue[]) {
+ /* Restore TSX features removed by -v2 above */
+ { "hle", "on" },
+ { "rtm", "on" },
+ { /* end of list */ }
+ },
+ },
{ /* end of list */ }
}
},
--
2.27.0