From 2da2a94f0ef5b6cf7fb8eacee1814a418d9bde74 Mon Sep 17 00:00:00 2001 From: Wenpeng Liang Date: Sat, 25 Dec 2021 17:42:53 +0800 Subject: libhns: Add new interfaces hr reg ***() to operate the CQE field Implement hr_reg_xxx() to simplify the code for filling or extracting fields. Signed-off-by: Wenpeng Liang --- providers/hns/hns_roce_u.h | 53 +++++++++++++++++++++++++ providers/hns/hns_roce_u_hw_v2.c | 58 ++++++++++------------------ providers/hns/hns_roce_u_hw_v2.h | 66 ++++++++++++-------------------- 3 files changed, 98 insertions(+), 79 deletions(-) diff --git a/providers/hns/hns_roce_u.h b/providers/hns/hns_roce_u.h index c1ae1c9..df7f485 100644 --- a/providers/hns/hns_roce_u.h +++ b/providers/hns/hns_roce_u.h @@ -101,6 +101,59 @@ #define roce_set_bit(origin, shift, val) \ roce_set_field((origin), (1ul << (shift)), (shift), (val)) +#define FIELD_LOC(field_type, field_h, field_l) \ + field_type, field_h, \ + field_l + BUILD_ASSERT_OR_ZERO(((field_h) / 32) == \ + ((field_l) / 32)) + +#define _hr_reg_enable(ptr, field_type, field_h, field_l) \ + ({ \ + const field_type *_ptr = ptr; \ + BUILD_ASSERT((field_h) == (field_l)); \ + *((__le32 *)_ptr + (field_h) / 32) |= \ + htole32(BIT((field_l) % 32)); \ + }) + +#define hr_reg_enable(ptr, field) _hr_reg_enable(ptr, field) + +#define _hr_reg_clear(ptr, field_type, field_h, field_l) \ + ({ \ + const field_type *_ptr = ptr; \ + BUILD_ASSERT((field_h) >= (field_l)); \ + *((__le32 *)_ptr + (field_h) / 32) &= \ + ~htole32(GENMASK((field_h) % 32, (field_l) % 32)); \ + }) + +#define hr_reg_clear(ptr, field) _hr_reg_clear(ptr, field) + +#define _hr_reg_write_bool(ptr, field_type, field_h, field_l, val) \ + ({ \ + (val) ? _hr_reg_enable(ptr, field_type, field_h, field_l) : \ + _hr_reg_clear(ptr, field_type, field_h, field_l);\ + }) + +#define hr_reg_write_bool(ptr, field, val) _hr_reg_write_bool(ptr, field, val) + +#define _hr_reg_write(ptr, field_type, field_h, field_l, val) \ + ({ \ + const uint32_t _val = val; \ + _hr_reg_clear(ptr, field_type, field_h, field_l); \ + *((__le32 *)ptr + (field_h) / 32) |= htole32(FIELD_PREP( \ + GENMASK((field_h) % 32, (field_l) % 32), _val)); \ + }) + +#define hr_reg_write(ptr, field, val) _hr_reg_write(ptr, field, val) + +#define _hr_reg_read(ptr, field_type, field_h, field_l) \ + ({ \ + const field_type *_ptr = ptr; \ + BUILD_ASSERT((field_h) >= (field_l)); \ + FIELD_GET(GENMASK((field_h) % 32, (field_l) % 32), \ + le32toh(*((__le32 *)_ptr + (field_h) / 32))); \ + }) + +#define hr_reg_read(ptr, field) _hr_reg_read(ptr, field) + enum { HNS_ROCE_QP_TABLE_BITS = 8, HNS_ROCE_QP_TABLE_SIZE = 1 << HNS_ROCE_QP_TABLE_BITS, diff --git a/providers/hns/hns_roce_u_hw_v2.c b/providers/hns/hns_roce_u_hw_v2.c index e7dec0b..558457a 100644 --- a/providers/hns/hns_roce_u_hw_v2.c +++ b/providers/hns/hns_roce_u_hw_v2.c @@ -187,8 +187,7 @@ static void handle_error_cqe(struct hns_roce_v2_cqe *cqe, struct ibv_wc *wc, } } - wc->vendor_err = roce_get_field(cqe->byte_16, CQE_BYTE_16_SUB_STATUS_M, - CQE_BYTE_16_SUB_STATUS_S); + wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); } static struct hns_roce_v2_cqe *get_cqe_v2(struct hns_roce_cq *cq, int entry) @@ -200,8 +199,8 @@ static void *get_sw_cqe_v2(struct hns_roce_cq *cq, int n) { struct hns_roce_v2_cqe *cqe = get_cqe_v2(cq, n & cq->ibv_cq.cqe); - return (!!(roce_get_bit(cqe->byte_4, CQE_BYTE_4_OWNER_S)) ^ - !!(n & (cq->ibv_cq.cqe + 1))) ? cqe : NULL; + return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & (cq->ibv_cq.cqe + 1))) ? + cqe : NULL; } static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *cq) @@ -257,8 +256,7 @@ static int get_srq_from_cqe(struct hns_roce_v2_cqe *cqe, uint32_t srqn; if (hr_qp->verbs_qp.qp.qp_type == IBV_QPT_XRC_RECV) { - srqn = roce_get_field(cqe->byte_12, CQE_BYTE_12_XRC_SRQN_M, - CQE_BYTE_12_XRC_SRQN_S); + srqn = hr_reg_read(cqe, CQE_XRC_SRQN); *srq = hns_roce_find_srq(ctx, srqn); if (!*srq) @@ -438,15 +436,13 @@ static int handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, struct ibv_wc *wc, (opcode == HNS_ROCE_RECV_OP_SEND || opcode == HNS_ROCE_RECV_OP_SEND_WITH_IMM || opcode == HNS_ROCE_RECV_OP_SEND_WITH_INV) && - (roce_get_bit(cqe->byte_4, CQE_BYTE_4_RQ_INLINE_S))) { + hr_reg_read(cqe, CQE_RQ_INLINE)) { struct hns_roce_rinl_sge *sge_list; uint32_t wr_num, wr_cnt, sge_num, data_len; uint8_t *wqe_buf; uint32_t sge_cnt, size; - wr_num = (uint16_t)roce_get_field(cqe->byte_4, - CQE_BYTE_4_WQE_IDX_M, - CQE_BYTE_4_WQE_IDX_S) & 0xffff; + wr_num = hr_reg_read(cqe, CQE_WQE_IDX); wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1); sge_list = (*cur_qp)->rq_rinl_buf.wqe_list[wr_cnt].sg_list; @@ -477,13 +473,10 @@ static int handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, struct ibv_wc *wc, static void parse_for_ud_qp(struct hns_roce_v2_cqe *cqe, struct ibv_wc *wc) { - wc->sl = roce_get_field(cqe->byte_32, CQE_BYTE_32_SL_M, - CQE_BYTE_32_SL_S); - wc->src_qp = roce_get_field(cqe->byte_32, CQE_BYTE_32_RMT_QPN_M, - CQE_BYTE_32_RMT_QPN_S); + wc->sl = hr_reg_read(cqe, CQE_SL); + wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); wc->slid = 0; - wc->wc_flags |= roce_get_bit(cqe->byte_32, CQE_BYTE_32_GRH_S) ? - IBV_WC_GRH : 0; + wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IBV_WC_GRH : 0; wc->pkey_index = 0; } @@ -492,8 +485,7 @@ static void parse_cqe_for_srq(struct hns_roce_v2_cqe *cqe, struct ibv_wc *wc, { uint32_t wqe_idx; - wqe_idx = roce_get_field(cqe->byte_4, CQE_BYTE_4_WQE_IDX_M, - CQE_BYTE_4_WQE_IDX_S); + wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); wc->wr_id = srq->wrid[wqe_idx & (srq->wqe_cnt - 1)]; hns_roce_free_srq_wqe(srq, wqe_idx); } @@ -533,8 +525,7 @@ static void parse_cqe_for_req(struct hns_roce_v2_cqe *cqe, struct ibv_wc *wc, * according to the wqe idx in the current cqe first */ if (hr_qp->sq_signal_bits) { - wqe_idx = roce_get_field(cqe->byte_4, CQE_BYTE_4_WQE_IDX_M, - CQE_BYTE_4_WQE_IDX_S); + wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); /* get the processed wqes num since last signalling */ wq->tail += (wqe_idx - wq->tail) & (wq->wqe_cnt - 1); } @@ -590,8 +581,7 @@ static int hns_roce_v2_poll_one(struct hns_roce_cq *cq, udma_from_device_barrier(); - qpn = roce_get_field(cqe->byte_16, CQE_BYTE_16_LCL_QPN_M, - CQE_BYTE_16_LCL_QPN_S); + qpn = hr_reg_read(cqe, CQE_LCL_QPN); /* if cur qp is null, then could not get the correct qpn */ if (!*cur_qp || qpn != (*cur_qp)->verbs_qp.qp.qp_num) { @@ -600,11 +590,9 @@ static int hns_roce_v2_poll_one(struct hns_roce_cq *cq, return V2_CQ_POLL_ERR; } - status = roce_get_field(cqe->byte_4, CQE_BYTE_4_STATUS_M, - CQE_BYTE_4_STATUS_S); - opcode = roce_get_field(cqe->byte_4, CQE_BYTE_4_OPCODE_M, - CQE_BYTE_4_OPCODE_S); - is_send = roce_get_bit(cqe->byte_4, CQE_BYTE_4_S_R_S) == CQE_FOR_SQ; + status = hr_reg_read(cqe, CQE_STATUS); + opcode = hr_reg_read(cqe, CQE_OPCODE); + is_send = hr_reg_read(cqe, CQE_S_R) == CQE_FOR_SQ; if (is_send) { parse_cqe_for_req(cqe, wc, *cur_qp, opcode); } else { @@ -1350,26 +1338,20 @@ static void __hns_roce_v2_cq_clean(struct hns_roce_cq *cq, uint32_t qpn, while ((int) --prod_index - (int) cq->cons_index >= 0) { cqe = get_cqe_v2(cq, prod_index & cq->ibv_cq.cqe); - if (roce_get_field(cqe->byte_16, CQE_BYTE_16_LCL_QPN_M, - CQE_BYTE_16_LCL_QPN_S) == qpn) { - is_recv_cqe = roce_get_bit(cqe->byte_4, - CQE_BYTE_4_S_R_S); + if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { + is_recv_cqe = hr_reg_read(cqe, CQE_S_R); if (srq && is_recv_cqe) { - wqe_index = roce_get_field(cqe->byte_4, - CQE_BYTE_4_WQE_IDX_M, - CQE_BYTE_4_WQE_IDX_S); + wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); hns_roce_free_srq_wqe(srq, wqe_index); } ++nfreed; } else if (nfreed) { dest = get_cqe_v2(cq, (prod_index + nfreed) & cq->ibv_cq.cqe); - owner_bit = roce_get_bit(dest->byte_4, - CQE_BYTE_4_OWNER_S); + owner_bit = hr_reg_read(dest, CQE_OWNER); memcpy(dest, cqe, cq->cqe_size); - roce_set_bit(dest->byte_4, CQE_BYTE_4_OWNER_S, - owner_bit); + hr_reg_write_bool(dest, CQE_OWNER, owner_bit); } } diff --git a/providers/hns/hns_roce_u_hw_v2.h b/providers/hns/hns_roce_u_hw_v2.h index e91b1f7..92e5f1a 100644 --- a/providers/hns/hns_roce_u_hw_v2.h +++ b/providers/hns/hns_roce_u_hw_v2.h @@ -154,47 +154,31 @@ struct hns_roce_v2_cqe { __le32 rsv[8]; }; -#define CQE_BYTE_4_OPCODE_S 0 -#define CQE_BYTE_4_OPCODE_M (((1UL << 5) - 1) << CQE_BYTE_4_OPCODE_S) - -#define CQE_BYTE_4_RQ_INLINE_S 5 - -#define CQE_BYTE_4_S_R_S 6 -#define CQE_BYTE_4_OWNER_S 7 - -#define CQE_BYTE_4_STATUS_S 8 -#define CQE_BYTE_4_STATUS_M (((1UL << 8) - 1) << CQE_BYTE_4_STATUS_S) - -#define CQE_BYTE_4_WQE_IDX_S 16 -#define CQE_BYTE_4_WQE_IDX_M (((1UL << 16) - 1) << CQE_BYTE_4_WQE_IDX_S) - -#define CQE_BYTE_12_XRC_SRQN_S 0 -#define CQE_BYTE_12_XRC_SRQN_M (((1UL << 24) - 1) << CQE_BYTE_12_XRC_SRQN_S) - -#define CQE_BYTE_16_LCL_QPN_S 0 -#define CQE_BYTE_16_LCL_QPN_M (((1UL << 24) - 1) << CQE_BYTE_16_LCL_QPN_S) - -#define CQE_BYTE_16_SUB_STATUS_S 24 -#define CQE_BYTE_16_SUB_STATUS_M (((1UL << 8) - 1) << CQE_BYTE_16_SUB_STATUS_S) - -#define CQE_BYTE_28_SMAC_S 0 -#define CQE_BYTE_28_SMAC_M (((1UL << 16) - 1) << CQE_BYTE_28_SMAC_S) - -#define CQE_BYTE_28_PORT_TYPE_S 16 -#define CQE_BYTE_28_PORT_TYPE_M (((1UL << 2) - 1) << CQE_BYTE_28_PORT_TYPE_S) - -#define CQE_BYTE_32_RMT_QPN_S 0 -#define CQE_BYTE_32_RMT_QPN_M (((1UL << 24) - 1) << CQE_BYTE_32_RMT_QPN_S) - -#define CQE_BYTE_32_SL_S 24 -#define CQE_BYTE_32_SL_M (((1UL << 3) - 1) << CQE_BYTE_32_SL_S) - -#define CQE_BYTE_32_PORTN_S 27 -#define CQE_BYTE_32_PORTN_M (((1UL << 3) - 1) << CQE_BYTE_32_PORTN_S) - -#define CQE_BYTE_32_GRH_S 30 - -#define CQE_BYTE_32_LPK_S 31 +#define CQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_cqe, h, l) + +#define CQE_OPCODE CQE_FIELD_LOC(4, 0) +#define CQE_RQ_INLINE CQE_FIELD_LOC(5, 5) +#define CQE_S_R CQE_FIELD_LOC(6, 6) +#define CQE_OWNER CQE_FIELD_LOC(7, 7) +#define CQE_STATUS CQE_FIELD_LOC(15, 8) +#define CQE_WQE_IDX CQE_FIELD_LOC(31, 16) +#define CQE_RKEY_IMMTDATA CQE_FIELD_LOC(63, 32) +#define CQE_XRC_SRQN CQE_FIELD_LOC(87, 64) +#define CQE_RSV0 CQE_FIELD_LOC(95, 88) +#define CQE_LCL_QPN CQE_FIELD_LOC(119, 96) +#define CQE_SUB_STATUS CQE_FIELD_LOC(127, 120) +#define CQE_BYTE_CNT CQE_FIELD_LOC(159, 128) +#define CQE_SMAC CQE_FIELD_LOC(207, 160) +#define CQE_PORT_TYPE CQE_FIELD_LOC(209, 208) +#define CQE_VID CQE_FIELD_LOC(221, 210) +#define CQE_VID_VLD CQE_FIELD_LOC(222, 222) +#define CQE_RSV2 CQE_FIELD_LOC(223, 223) +#define CQE_RMT_QPN CQE_FIELD_LOC(247, 224) +#define CQE_SL CQE_FIELD_LOC(250, 248) +#define CQE_PORTN CQE_FIELD_LOC(253, 251) +#define CQE_GRH CQE_FIELD_LOC(254, 254) +#define CQE_LPK CQE_FIELD_LOC(255, 255) +#define CQE_RSV3 CQE_FIELD_LOC(511, 256) struct hns_roce_rc_sq_wqe { __le32 byte_4; -- 2.27.0