veega2022
d97a7bc7ab
add hikptool roce/roh/cxl/serdes/socip/pcie features source code
...
add support hikptool roce/roh/cxl/serdes/socip/pcie dfx cmd
Signed-off-by: veega2022 <zhuweijia@huawei.com>
Signed-off-by: shushengming <shushengming1@huawei.com>
Signed-off-by: wangkang <wangkang124@hisilicon.com>
Signed-off-by: fangjian <f.fangjian@huawei.com>
Signed-off-by: hesiyuan <hesiyuan4@huawei.com>
(cherry picked from commit 46da047b4fa49bc8268b031081e9c4b6b09fddcc)
2022-10-28 15:17:19 +08:00
openeuler-ci-bot
495206c367
!2 [sync] PR-1: 初始hikptool仓库，新增spec文件和第一版源码
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From: @openeuler-sync-bot
Reviewed-by: @kongzizaixian
Signed-off-by: @kongzizaixian
2022-10-18 06:12:49 +00:00
veega2022
ceee18228a
init repo with spec and source code
...
first add hikptool spec and source code, first version is 1.0.0
Signed-off-by: veega2022 <zhuweijia@huawei.com>
(cherry picked from commit 4d5465ee95b986b7a9e57fadb2fbdc9464c1a55d)
2022-10-17 15:39:06 +08:00
openeuler-ci-bot
ef391f2c26
Initial commit
2022-10-12 02:05:10 +00:00
