!284 add l4 support

From: @yzyssdd Reviewed-by: @li-yancheng, @huang-xiaoquan Signed-off-by: @li-yancheng
add l4 support
2024-05-29 13:20:13 +00:00 · 2024-05-29 14:28:25 +08:00 · 2024-03-21 11:19:08 +00:00 · 2024-03-21 16:17:20 +08:00 · 2024-03-20 01:07:52 +00:00 · 2024-03-08 15:14:40 +08:00
57 changed files with 78870 additions and 72 deletions
--- a/AVX512-0001-x86-Add-int1-as-one-byte-opcode-0xf1.patch
+++ b/AVX512-0001-x86-Add-int1-as-one-byte-opcode-0xf1.patch
--- a/AVX512-0002-x86-drop-OP_Mask.patch
+++ b/AVX512-0002-x86-drop-OP_Mask.patch
--- a/AVX512-0003-x86-correct-VCVT-U-SI2SD-rounding-mode-handling.patch
+++ b/AVX512-0003-x86-correct-VCVT-U-SI2SD-rounding-mode-handling.patch
--- a/AVX512-0004-x86-64-generalize-OP_G-s-EVEX.R-handling.patch
+++ b/AVX512-0004-x86-64-generalize-OP_G-s-EVEX.R-handling.patch
--- a/AVX512-0005-x86-64-properly-bounds-check-bnd-N-in-OP_G.patch
+++ b/AVX512-0005-x86-64-properly-bounds-check-bnd-N-in-OP_G.patch
--- a/AVX512-0006-x86-fold-duplicate-register-printing-code.patch
+++ b/AVX512-0006-x86-fold-duplicate-register-printing-code.patch
--- a/AVX512-0007-x86-fold-duplicate-code-in-MOVSXD_Fixup.patch
+++ b/AVX512-0007-x86-fold-duplicate-code-in-MOVSXD_Fixup.patch
--- a/AVX512-0008-x86-correct-EVEX.V-handling-outside-of-64-bit-mode.patch
+++ b/AVX512-0008-x86-correct-EVEX.V-handling-outside-of-64-bit-mode.patch
--- a/AVX512-0009-x86-drop-vex_mode-and-vex_scalar_mode.patch
+++ b/AVX512-0009-x86-drop-vex_mode-and-vex_scalar_mode.patch
--- a/AVX512-0010-x86-fold-duplicate-vector-register-printing-code.patch
+++ b/AVX512-0010-x86-fold-duplicate-vector-register-printing-code.patch
--- a/AVX512-0011-x86-drop-xmm_m-b-w-d-q-_mode.patch
+++ b/AVX512-0011-x86-drop-xmm_m-b-w-d-q-_mode.patch
--- a/AVX512-0012-x86-drop-vex_scalar_w_dq_mode.patch
+++ b/AVX512-0012-x86-drop-vex_scalar_w_dq_mode.patch
--- a/AVX512-0013-x86-drop-dq-b-d-_mode.patch
+++ b/AVX512-0013-x86-drop-dq-b-d-_mode.patch
--- a/AVX512-0014-x86-express-unduly-set-rounding-control-bits-in-disa.patch
+++ b/AVX512-0014-x86-express-unduly-set-rounding-control-bits-in-disa.patch
--- a/AVX512-0015-x86-Simplify-check-for-distinct-TMM-register-operand.patch
+++ b/AVX512-0015-x86-Simplify-check-for-distinct-TMM-register-operand.patch
--- a/AVX512-0016-PATCH-1-2-Enable-Intel-AVX512_FP16-instructions.patch
+++ b/AVX512-0016-PATCH-1-2-Enable-Intel-AVX512_FP16-instructions.patch
--- a/AVX512-0017-PATCH-2-2-Add-tests-for-Intel-AVX512_FP16-instructio.patch
+++ b/AVX512-0017-PATCH-2-2-Add-tests-for-Intel-AVX512_FP16-instructio.patch
--- a/AVX512-0018-x86-ELF-fix-.tfloat-output.patch
+++ b/AVX512-0018-x86-ELF-fix-.tfloat-output.patch
--- a/AVX512-0019-x86-ELF-fix-.ds.x-output.patch
+++ b/AVX512-0019-x86-ELF-fix-.ds.x-output.patch
--- a/AVX512-0020-x86-ELF-fix-.tfloat-output-with-hex-input.patch
+++ b/AVX512-0020-x86-ELF-fix-.tfloat-output-with-hex-input.patch
--- a/AVX512-0021-x86-introduce-.hfloat-directive.patch
+++ b/AVX512-0021-x86-introduce-.hfloat-directive.patch
--- a/AVX512-0022-x86-Avoid-abort-on-invalid-broadcast.patch
+++ b/AVX512-0022-x86-Avoid-abort-on-invalid-broadcast.patch
--- a/AVX512-0023-x86-Put-back-3-aborts-in-OP_E_memory.patch
+++ b/AVX512-0023-x86-Put-back-3-aborts-in-OP_E_memory.patch
--- a/AVX512-0024-x86-Print-bad-on-invalid-broadcast-in-OP_E_memory.patch
+++ b/AVX512-0024-x86-Print-bad-on-invalid-broadcast-in-OP_E_memory.patch
--- a/AVX512-0025-x86-Terminate-mnemonicendp-in-swap_operand.patch
+++ b/AVX512-0025-x86-Terminate-mnemonicendp-in-swap_operand.patch
--- a/AVX512-0026-opcodes-Make-i386-dis.c-thread-safe.patch
+++ b/AVX512-0026-opcodes-Make-i386-dis.c-thread-safe.patch
--- a/AVX512-0027-x86-reduce-AVX512-FP16-set-of-insns-decoded-through-.patch
+++ b/AVX512-0027-x86-reduce-AVX512-FP16-set-of-insns-decoded-through-.patch
--- a/AVX512-0028-x86-reduce-AVX512-FP-set-of-insns-decoded-through-ve.patch
+++ b/AVX512-0028-x86-reduce-AVX512-FP-set-of-insns-decoded-through-ve.patch
--- a/AVX512-0029-x86-consistently-use-scalar_mode-for-AVX512-FP16-sca.patch
+++ b/AVX512-0029-x86-consistently-use-scalar_mode-for-AVX512-FP16-sca.patch
--- a/LoongArch-Fix-PLT-entry-generate-bug.patch
+++ b/LoongArch-Fix-PLT-entry-generate-bug.patch
@ -0,0 +1,35 @@
+diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c
+index a623aa32..dc9f4e49 100644
+--- a/bfd/elfnn-loongarch.c
+++ b/bfd/elfnn-loongarch.c
+@@ -980,7 +980,7 @@ loongarch_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
+      (although we could actually do it here).  */
+   if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
+     {
+-      if (h->plt.refcount < 0
+      if (h->plt.refcount <= 0
+ 	  || (h->type != STT_GNU_IFUNC
+ 	      && (SYMBOL_REFERENCES_LOCAL (info, h)
+ 		  || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
+@@ -993,8 +993,6 @@ loongarch_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
+ 	  h->plt.offset = MINUS_ONE;
+ 	  h->needs_plt = 0;
+ 	}
+-      else
+-	h->needs_plt = 1;
+ 
+       return true;
+     }
+diff --git a/ld/testsuite/ld-elf/shared.exp b/ld/testsuite/ld-elf/shared.exp
+index 8b7069c2..718416b0 100644
+--- a/ld/testsuite/ld-elf/shared.exp
+++ b/ld/testsuite/ld-elf/shared.exp
+@@ -502,7 +502,7 @@ run_ld_link_tests [list \
+ # but that is just an optimization so don't complain loudly.
+ setup_xfail *-*-*
+ clear_xfail alpha-*-* bfin-*-linux* csky-*-* frv-*-* hppa*-*-* i?86-*-*
+-clear_xfail ia64-*-* microblaze-*-* powerpc*-*-* x86_64-*-* xtensa-*-*
+clear_xfail ia64-*-* loongarch*-*-* microblaze-*-* powerpc*-*-* x86_64-*-* xtensa-*-*
+ run_ld_link_tests {
+     {"pr22374 function pointer initialization"
+ 	"" "tmpdir/pr22374.so" "" "pr22374a.s"
--- a/LoongArch-Fixup-check-file-for-ifunc-reloc.patch
+++ b/LoongArch-Fixup-check-file-for-ifunc-reloc.patch
@ -0,0 +1,26 @@
+From 7ba7aee2bc5b2df22fdba26c436e64b1bc9e735a Mon Sep 17 00:00:00 2001
+From: XingLi <lixing@loongson.cn>
+Date: Wed, 26 Jul 2023 15:28:31 +0800
+Subject: [PATCH 3/3] Fixup check file for ifunc reloc
+
+---
+ ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d b/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d
+index 29f2d3f3..3723326b 100644
+--- a/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d
+++ b/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d
+@@ -5,6 +5,6 @@
+ .*: +file format .*
+ 
+ DYNAMIC RELOCATION RECORDS
+-OFFSET +TYPE +VALUE
+-[[:xdigit:]]+ R_LARCH_IRELATIVE +\*ABS\*\+0x[[:xdigit:]]+
+-[[:xdigit:]]+ R_LARCH_64 +test
+OFFSET +TYPE +VALUE 
+[[:xdigit:]]+ R_LARCH_IRELATIVE  +\*ABS\*\+0x[[:xdigit:]]+
+[[:xdigit:]]+ R_LARCH_64        +test+
+-- 
+2.27.0
+
--- a/LoongArch-Fixup-gas-check-illegal-for-b-label.patch
+++ b/LoongArch-Fixup-gas-check-illegal-for-b-label.patch
@ -0,0 +1,26 @@
+From 70a4a09cc223d761b261859fbf21af578894d776 Mon Sep 17 00:00:00 2001
+From: XingLi <lixing@loongson.cn>
+Date: Sat, 22 Jul 2023 15:49:36 +0800
+Subject: [PATCH 2/3] Fixup gas check illegal for 'b label'
+
+---
+ opcodes/loongarch-opc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
+index be0de61c..e3833007 100644
+--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
+@@ -823,8 +823,8 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] =
+   { 0x0,	0x0,		"bnez",		"r,la",				"bnez %1,%%b21(%2)",		0, 0, 0 },
+   { 0x44000000, 0xfc000000,	"bnez",		"r5:5,sb0:5|10:16<<2",		0,				0, 0, 0 },
+   { 0x0,	0x0,		"jr",		"r",				"jirl $r0,%1,0",		0, 0, 0 },
+-  { 0x50000000, 0xfc000000,	"b",		"sb0:10|10:16<<2",		0,				0, 0, 0 },
+   { 0x0,	0x0,		"b",		"la",				"b %%b26(%1)",			0, 0, 0 },
+  { 0x50000000, 0xfc000000,	"b",		"sb0:10|10:16<<2",		0,				0, 0, 0 },
+   { 0x4c000000, 0xfc000000,	"jirl",		"r0:5,r5:5,s10:16<<2",		0,				0, 0, 0 },
+   { 0x0,	0x0,		"bl",		"la",				"bl %%b26(%1)",			0, 0, 0 },
+   { 0x54000000, 0xfc000000,	"bl",		"sb0:10|10:16<<2",		0,				0, 0, 0 },
+-- 
+2.27.0
+
--- a/LoongArch-Fixup-unresolve-symbols-problem.patch
+++ b/LoongArch-Fixup-unresolve-symbols-problem.patch
@ -0,0 +1,117 @@
+From 534cfca985709515f4871f0aa1efc57c4e274a1a Mon Sep 17 00:00:00 2001
+From: yala <zhaojunchao@loongson.cn>
+Date: Fri, 3 Mar 2023 11:19:40 +0800
+Subject: [PATCH] ld:Fix option unresolved-symbols=ignore-all does not work
+ when LARCH_64 appears alone
+
+Change-Id: Id06b7b77deefa64a2ea2c9f10a63130e5e4aaf65
+---
+ bfd/elfnn-loongarch.c                         | 11 +++++---
+ ld/testsuite/ld-undefined/undefine-ignored.c  | 10 +++++++
+ .../ld-undefined/undefine-ignored.exp         | 26 +++++++++++++++++++
+ 3 files changed, 43 insertions(+), 4 deletions(-)
+ create mode 100644 ld/testsuite/ld-undefined/undefine-ignored.c
+ create mode 100644 ld/testsuite/ld-undefined/undefine-ignored.exp
+
+diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c
+index 459dd0df..5bf528b9 100644
+--- a/bfd/elfnn-loongarch.c
+++ b/bfd/elfnn-loongarch.c
+@@ -1201,7 +1201,8 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf)
+ 	}
+     }
+ 
+-  if (h->root.type == bfd_link_hash_undefweak)
+  if (h->root.type == bfd_link_hash_undefweak ||
+      h->root.type == bfd_link_hash_undefined)
+     {
+       if (UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)
+ 	  || ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
+@@ -1211,7 +1212,8 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf)
+ 	{
+ 	  /* Make sure this symbol is output as a dynamic symbol.
+ 	     Undefined weak syms won't yet be marked as dynamic.  */
+-	  if (!bfd_elf_link_record_dynamic_symbol (info, h))
+	  if (h->root.type == bfd_link_hash_undefweak &&
+              !bfd_elf_link_record_dynamic_symbol (info, h))
+ 	    return false;
+ 
+ 	  if (h->dynindx == -1)
+@@ -2303,6 +2305,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
+       char tls_type;
+       bfd_vma relocation, off, ie_off;
+       int i, j;
+      bool ignored = false;
+ 
+       howto = loongarch_elf_rtype_to_howto (input_bfd, r_type);
+       if (howto == NULL || r_type == R_LARCH_GNU_VTINHERIT
+@@ -2344,8 +2347,8 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
+ 	}
+       else
+ 	{
+-	  bool warned, ignored;
+ 
+      bool warned;
+ 	  RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
+ 				   r_symndx, symtab_hdr, sym_hashes,
+ 				   h, sec, relocation,
+@@ -2497,7 +2500,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
+ 		{
+ 		  if (h->dynindx == -1)
+ 		    {
+-		      if (h->root.type == bfd_link_hash_undefined)
+		      if (h->root.type == bfd_link_hash_undefined && !ignored)
+ 			(*info->callbacks->undefined_symbol)
+ 			  (info, name, input_bfd, input_section,
+ 			   rel->r_offset, true);
+diff --git a/ld/testsuite/ld-undefined/undefine-ignored.c b/ld/testsuite/ld-undefined/undefine-ignored.c
+new file mode 100644
+index 00000000..7955df04
+--- /dev/null
+++ b/ld/testsuite/ld-undefined/undefine-ignored.c
+@@ -0,0 +1,10 @@
+#include <stdio.h>
+// a is R_LARCH_64 type
+extern struct wl_interface a;
+
+struct wl_interface * b = &a;
+
+int main(void)
+{
+    return 0;
+}
+diff --git a/ld/testsuite/ld-undefined/undefine-ignored.exp b/ld/testsuite/ld-undefined/undefine-ignored.exp
+new file mode 100644
+index 00000000..7975fbdc
+--- /dev/null
+++ b/ld/testsuite/ld-undefined/undefine-ignored.exp
+@@ -0,0 +1,26 @@
+set testund "undefined-ignored"
+set testfn "undefined-ignored function"
+set testline "undefined-ignored line"
+
+if [istarget loongarch*-*-*] {
+    if { ![is_remote host] && [which $CC] == 0 } {
+        verbose "Could not find C compiler!" 1
+            untested $testund
+            untested $testfn
+            untested $testline
+    } elseif { ![ld_compile "$CC -c" "$srcdir/$subdir/undefine-ignored.c" \
+                 tmpdir/undefine-ignored.o] } {
+        verbose "Unable to compile test file!" 1
+            unresolved $testund
+            unresolved $testfn
+            unresolved $testline
+    }
+
+    if { ![is_elf_format] } then {
+        unsupported $testname
+    } elseif {![ld_link $ld tmpdir/a.out \
+        "-e main --unresolved-symbols=ignore-all tmpdir/undefine-ignored.o"]} then {
+            verbose "ld faile"
+            fail $testname
+        }
+}
+-- 
+2.27.0
+
--- a/LoongArch-binutils-Add-LoongArch-support.patch
+++ b/LoongArch-binutils-Add-LoongArch-support.patch
--- a/LoongArch-gas-add-support-using-constant-variable-in.patch
+++ b/LoongArch-gas-add-support-using-constant-variable-in.patch
@ -0,0 +1,506 @@
+From 31896a5e1105c4d5c1954750c6145fbab040430d Mon Sep 17 00:00:00 2001
+From: tangxiaolin <tangxiaolin@loongson.cn>
+Date: Wed, 17 Aug 2022 15:12:43 +0800
+Subject: [PATCH 1/3] LoongArch: gas: add support using constant variable in
+ instructions.
+
+        Instructions that can load immediate support using constant
+        variable like ".equ var, 123    li.w/d resgister, var".
+
+gas/
+        * config/loongarch-parse.y
+        * config/tc-loongarch.c
+
+        Add four testcases.One is a program using constant variable,
+        one test using label is unsupported, and another two test
+        almost instructions that can load immediate.
+
+gas/
+        * testsuite/gas/loongarch/li.d
+        * testsuite/gas/loongarch/li.s
+        * testsuite/gas/loongarch/imm_ins_label-fail.d
+        * testsuite/gas/loongarch/imm_ins_label-fail.l
+        * testsuite/gas/loongarch/imm_ins_label-fail.s
+        * testsuite/gas/loongarch/imm_ins.d
+        * testsuite/gas/loongarch/imm_ins.s
+        * testsuite/gas/loongarch/imm_ins_32.d
+        * testsuite/gas/loongarch/imm_ins_32.s
+---
+ gas/config/loongarch-parse.y                  | 20 +++++
+ gas/config/tc-loongarch.c                     | 18 ----
+ gas/testsuite/gas/loongarch/imm_ins.d         | 80 ++++++++++++++++++
+ gas/testsuite/gas/loongarch/imm_ins.s         | 83 +++++++++++++++++++
+ gas/testsuite/gas/loongarch/imm_ins_32.d      | 57 +++++++++++++
+ gas/testsuite/gas/loongarch/imm_ins_32.s      | 60 ++++++++++++++
+ .../gas/loongarch/imm_ins_label-fail.d        |  3 +
+ .../gas/loongarch/imm_ins_label-fail.l        |  3 +
+ .../gas/loongarch/imm_ins_label-fail.s        |  3 +
+ gas/testsuite/gas/loongarch/li.d              | 21 +++++
+ gas/testsuite/gas/loongarch/li.s              | 22 +++++
+ 11 files changed, 352 insertions(+), 18 deletions(-)
+ create mode 100644 gas/testsuite/gas/loongarch/imm_ins.d
+ create mode 100644 gas/testsuite/gas/loongarch/imm_ins.s
+ create mode 100644 gas/testsuite/gas/loongarch/imm_ins_32.d
+ create mode 100644 gas/testsuite/gas/loongarch/imm_ins_32.s
+ create mode 100644 gas/testsuite/gas/loongarch/imm_ins_label-fail.d
+ create mode 100644 gas/testsuite/gas/loongarch/imm_ins_label-fail.l
+ create mode 100644 gas/testsuite/gas/loongarch/imm_ins_label-fail.s
+ create mode 100644 gas/testsuite/gas/loongarch/li.d
+ create mode 100644 gas/testsuite/gas/loongarch/li.s
+
+diff --git a/gas/config/loongarch-parse.y b/gas/config/loongarch-parse.y
+index 902d7204..87046877 100644
+--- a/gas/config/loongarch-parse.y
+++ b/gas/config/loongarch-parse.y
+@@ -100,6 +100,25 @@ my_getExpression (expressionS *ep, const char *str)
+   return ret;
+ }
+ 
+static void
+emit_const_var (const char *op)
+{
+  expressionS ep;
+
+  if (end <= top)
+    as_fatal (_("expr too huge"));
+
+  my_getExpression (&ep, op);
+
+  if (ep.X_op != O_constant)
+    as_bad ("illegal operand: %s", op);
+
+  top->value.X_op = O_constant;
+  top->value.X_add_number = ep.X_add_number;
+  top->type = BFD_RELOC_LARCH_SOP_PUSH_ABSOLUTE;
+  top++;
+}
+
+ static void
+ reloc (const char *op_c_str, const char *id_c_str, offsetT addend)
+ {
+@@ -318,6 +337,7 @@ offsetT imm;
+ 
+ primary_expression
+ 	: INTEGER {emit_const ($1);}
+	| IDENTIFIER {emit_const_var ($1);}
+ 	| '(' expression ')'
+ 	| '%' IDENTIFIER '(' IDENTIFIER addend ')' {reloc ($2, $4, $5); free ($2); free ($4);}
+ 	| '%' IDENTIFIER '(' INTEGER addend ')' {reloc ($2, NULL, $4 + $5); free ($2);}
+diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
+index 93412b69..1e0d5ab5 100644
+--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
+@@ -582,24 +582,6 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
+       if (!ip->match_now)
+ 	break;
+ 
+-      if (esc_ch1 == 's')
+-	switch (esc_ch2)
+-	  {
+-	  case 'c':
+-	    ip->match_now = reloc_num == 0;
+-	    break;
+-	  }
+-      else
+-	switch (esc_ch2)
+-	  {
+-	  case 'c':
+-	    ip->match_now = reloc_num == 0 && 0 <= imm;
+-	    break;
+-	  }
+-
+-      if (!ip->match_now)
+-	break;
+-
+       ret = imm;
+       if (reloc_num)
+ 	{
+diff --git a/gas/testsuite/gas/loongarch/imm_ins.d b/gas/testsuite/gas/loongarch/imm_ins.d
+new file mode 100644
+index 00000000..0ceaead3
+--- /dev/null
+++ b/gas/testsuite/gas/loongarch/imm_ins.d
+@@ -0,0 +1,80 @@
+#as:
+#objdump: -dr
+#skip: loongarch32-*-*
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+00000000.* <.text>:
+[ 	]+0:[ 	]+03848c0c[ 	]+ori[ 	]+\$t0,[ 	]+\$zero,[ 	]+0x123
+[ 	]+4:[ 	]+15ffe00d[ 	]+lu12i.w[ 	]+\$t1,[ 	]+-256\(0xfff00\)
+[ 	]+8:[ 	]+16001fed[ 	]+lu32i.d[ 	]+\$t1,[ 	]+255\(0xff\)
+[ 	]+c:[ 	]+02bffc0e[ 	]+addi.w[ 	]+\$t2,[ 	]+\$zero,[ 	]+-1\(0xfff\)
+[ 	]+10:[ 	]+1601ffee[ 	]+lu32i.d[ 	]+\$t2,[ 	]+4095\(0xfff\)
+[ 	]+14:[ 	]+0004b58b[ 	]+alsl.w[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+18:[ 	]+0006b58b[ 	]+alsl.wu[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+1c:[ 	]+0009358b[ 	]+bytepick.w[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+20:[ 	]+000d358b[ 	]+bytepick.d[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+24:[ 	]+002a0002[ 	]+break[ 	]+0x2
+[ 	]+28:[ 	]+002a8002[ 	]+dbcl[ 	]+0x2
+[ 	]+2c:[ 	]+002b0002[ 	]+syscall[ 	]+0x2
+[ 	]+30:[ 	]+002cb58b[ 	]+alsl.d[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+34:[ 	]+0040898b[ 	]+slli.w[ 	]+\$a7,[ 	]+\$t0,[ 	]+0x2
+[ 	]+38:[ 	]+0041098b[ 	]+slli.d[ 	]+\$a7,[ 	]+\$t0,[ 	]+0x2
+[ 	]+3c:[ 	]+0044898b[ 	]+srli.w[ 	]+\$a7,[ 	]+\$t0,[ 	]+0x2
+[ 	]+40:[ 	]+004509ac[ 	]+srli.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+44:[ 	]+004889ac[ 	]+srai.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+48:[ 	]+004909ac[ 	]+srai.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+4c:[ 	]+006209ac[ 	]+bstrins.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2,[ 	]+0x2
+[ 	]+50:[ 	]+008209ac[ 	]+bstrins.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2,[ 	]+0x2
+[ 	]+54:[ 	]+00c209ac[ 	]+bstrpick.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2,[ 	]+0x2
+[ 	]+58:[ 	]+00c209ac[ 	]+bstrpick.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2,[ 	]+0x2
+[ 	]+5c:[ 	]+02048dac[ 	]+slti[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
+[ 	]+60:[ 	]+02448dac[ 	]+sltui[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
+[ 	]+64:[ 	]+02848dac[ 	]+addi.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
+[ 	]+68:[ 	]+02c48dac[ 	]+addi.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
+[ 	]+6c:[ 	]+03048dac[ 	]+lu52i.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
+[ 	]+70:[ 	]+034009ac[ 	]+andi[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+74:[ 	]+038009ac[ 	]+ori[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+78:[ 	]+03c009ac[ 	]+xori[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+7c:[ 	]+100009ac[ 	]+addu16i.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+2\(0x2\)
+[ 	]+80:[ 	]+1400246c[ 	]+lu12i.w[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+84:[ 	]+1600246c[ 	]+lu32i.d[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+88:[ 	]+1800246c[ 	]+pcaddi[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+8c:[ 	]+1a00246c[ 	]+pcalau12i[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+90:[ 	]+1c00246c[ 	]+pcaddu12i[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+94:[ 	]+1e00246c[ 	]+pcaddu18i[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+98:[ 	]+04048c0c[ 	]+csrrd[ 	]+\$t0,[ 	]+0x123
+[ 	]+9c:[ 	]+04048c2c[ 	]+csrwr[ 	]+\$t0,[ 	]+0x123
+[ 	]+a0:[ 	]+040009ac[ 	]+csrxchg[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+a4:[ 	]+060009a2[ 	]+cacop[ 	]+0x2,[ 	]+\$t1,[ 	]+2\(0x2\)
+[ 	]+a8:[ 	]+064009ac[ 	]+lddir[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+ac:[ 	]+06440980[ 	]+ldpte[ 	]+\$t0,[ 	]+0x2
+[ 	]+b0:[ 	]+0649b9a2[ 	]+invtlb[ 	]+0x2,[ 	]+\$t1,[ 	]+\$t2
+[ 	]+b4:[ 	]+200101ac[ 	]+ll.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+b8:[ 	]+210101ac[ 	]+sc.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+bc:[ 	]+220101ac[ 	]+ll.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+c0:[ 	]+230101ac[ 	]+sc.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+c4:[ 	]+240101ac[ 	]+ldptr.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+c8:[ 	]+250101ac[ 	]+stptr.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+cc:[ 	]+260101ac[ 	]+ldptr.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+d0:[ 	]+270101ac[ 	]+stptr.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+d4:[ 	]+280401ac[ 	]+ld.b[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+d8:[ 	]+284401ac[ 	]+ld.h[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+dc:[ 	]+288401ac[ 	]+ld.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+e0:[ 	]+28c401ac[ 	]+ld.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+e4:[ 	]+290401ac[ 	]+st.b[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+e8:[ 	]+294401ac[ 	]+st.h[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+ec:[ 	]+298401ac[ 	]+st.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+f0:[ 	]+29c401ac[ 	]+st.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+f4:[ 	]+2a0401ac[ 	]+ld.bu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+f8:[ 	]+2a4401ac[ 	]+ld.hu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+fc:[ 	]+2a8401ac[ 	]+ld.wu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+100:[ 	]+2ac401a2[ 	]+preld[ 	]+0x2,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+104:[ 	]+382c39a2[ 	]+preldx[ 	]+0x2,[ 	]+\$t1,[ 	]+\$t2
+[ 	]+108:[ 	]+2b048d8a[ 	]+fld.s[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+10c:[ 	]+2b448d8a[ 	]+fst.s[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+110:[ 	]+2b848d8a[ 	]+fld.d[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+114:[ 	]+2bc48d8a[ 	]+fst.d[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291\(0x123\)
+diff --git a/gas/testsuite/gas/loongarch/imm_ins.s b/gas/testsuite/gas/loongarch/imm_ins.s
+new file mode 100644
+index 00000000..f6a4e745
+--- /dev/null
+++ b/gas/testsuite/gas/loongarch/imm_ins.s
+@@ -0,0 +1,83 @@
+.equ a, 0x123
+.equ b, 0xfffff00000
+.equ c, 0xfffffffffff
+.equ d, 2
+.equ e,0x100
+
+li.w $r12, a
+li.d $r13, b
+li.d $r14, c
+
+alsl.w $r11,$r12,$r13,d
+alsl.wu $r11,$r12,$r13,d
+bytepick.w $r11,$r12,$r13,d
+bytepick.d $r11,$r12,$r13,d
+
+break d
+dbcl d
+syscall d
+
+alsl.d $r11,$r12, $r13,d
+slli.w $r11,$r12,d
+slli.d $r11,$r12,d
+srli.w $r11,$r12,d
+srli.d $r12,$r13,d
+srai.w $r12,$r13,d
+srai.d $r12,$r13,d
+
+bstrins.w $r12,$r13,d,d
+bstrins.d $r12,$r13,d,d
+bstrpick.d $r12,$r13,d,d
+bstrpick.d $r12,$r13,d,d
+
+slti $r12,$r13,a
+sltui $r12,$r13,a
+addi.w $r12,$r13,a
+addi.d $r12,$r13,a
+lu52i.d $r12,$r13,a
+andi $r12,$r13,d
+ori  $r12,$r13,d
+xori $r12,$r13,d
+addu16i.d $r12,$r13,d
+lu12i.w $r12,a
+lu32i.d $r12,a
+pcaddi $r12,a
+pcalau12i $r12,a
+pcaddu12i $r12,a
+pcaddu18i $r12,a
+
+csrrd $r12,a
+csrwr $r12,a
+csrxchg $r12,$r13,d
+cacop d,$r13,d
+lddir $r12,$r13,d
+ldpte $r12,d
+
+invtlb d,$r13,$r14
+
+ll.w $r12,$r13,e
+sc.w $r12,$r13,e
+ll.d $r12,$r13,e
+sc.d $r12,$r13,e
+ldptr.w $r12,$r13,e
+stptr.w $r12,$r13,e
+ldptr.d $r12,$r13,e
+stptr.d $r12,$r13,e
+ld.b $r12,$r13,e
+ld.h $r12,$r13,e
+ld.w $r12,$r13,e
+ld.d $r12,$r13,e
+st.b $r12,$r13,e
+st.h $r12,$r13,e
+st.w $r12,$r13,e
+st.d $r12,$r13,e
+ld.bu $r12,$r13,e
+ld.hu $r12,$r13,e
+ld.wu $r12,$r13,e
+preld d,$r13,e
+preldx d,$r13,$r14
+
+fld.s $f10,$r12,a
+fst.s $f10,$r12,a
+fld.d $f10,$r12,a
+fst.d $f10,$r12,a
+diff --git a/gas/testsuite/gas/loongarch/imm_ins_32.d b/gas/testsuite/gas/loongarch/imm_ins_32.d
+new file mode 100644
+index 00000000..0a826bfb
+--- /dev/null
+++ b/gas/testsuite/gas/loongarch/imm_ins_32.d
+@@ -0,0 +1,57 @@
+#as:
+#objdump: -dr
+#skip: loongarch64-*-*
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+00000000.* <.text>:
+[ 	]+0:[ 	]+03848c0c[ 	]+ori[ 	]+\$t0,[ 	]+\$zero,[ 	]+0x123
+[ 	]+4:[ 	]+0004b58b[ 	]+alsl.w[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+8:[ 	]+0006b58b[ 	]+alsl.wu[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+c:[ 	]+0009358b[ 	]+bytepick.w[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+10:[ 	]+002a0002[ 	]+break[ 	]+0x2
+[ 	]+14:[ 	]+002a8002[ 	]+dbcl[ 	]+0x2
+[ 	]+18:[ 	]+002b0002[ 	]+syscall[ 	]+0x2
+[ 	]+1c:[ 	]+0040898b[ 	]+slli.w[ 	]+\$a7,[ 	]+\$t0,[ 	]+0x2
+[ 	]+20:[ 	]+0044898b[ 	]+srli.w[ 	]+\$a7,[ 	]+\$t0,[ 	]+0x2
+[ 	]+24:[ 	]+004889ac[ 	]+srai.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+28:[ 	]+006209ac[ 	]+bstrins.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2,[ 	]+0x2
+[ 	]+2c:[ 	]+02048dac[ 	]+slti[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
+[ 	]+30:[ 	]+02448dac[ 	]+sltui[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
+[ 	]+34:[ 	]+02848dac[ 	]+addi.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
+[ 	]+38:[ 	]+034009ac[ 	]+andi[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+3c:[ 	]+038009ac[ 	]+ori[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+40:[ 	]+03c009ac[ 	]+xori[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+44:[ 	]+1400246c[ 	]+lu12i.w[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+48:[ 	]+1800246c[ 	]+pcaddi[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+4c:[ 	]+1a00246c[ 	]+pcalau12i[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+50:[ 	]+1c00246c[ 	]+pcaddu12i[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+54:[ 	]+1e00246c[ 	]+pcaddu18i[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+58:[ 	]+04048c0c[ 	]+csrrd[ 	]+\$t0,[ 	]+0x123
+[ 	]+5c:[ 	]+04048c2c[ 	]+csrwr[ 	]+\$t0,[ 	]+0x123
+[ 	]+60:[ 	]+040009ac[ 	]+csrxchg[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+64:[ 	]+060009a2[ 	]+cacop[ 	]+0x2,[ 	]+\$t1,[ 	]+2\(0x2\)
+[ 	]+68:[ 	]+064009ac[ 	]+lddir[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
+[ 	]+6c:[ 	]+06440980[ 	]+ldpte[ 	]+\$t0,[ 	]+0x2
+[ 	]+70:[ 	]+0649b9a2[ 	]+invtlb[ 	]+0x2,[ 	]+\$t1,[ 	]+\$t2
+[ 	]+74:[ 	]+200101ac[ 	]+ll.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+78:[ 	]+210101ac[ 	]+sc.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+7c:[ 	]+220101ac[ 	]+ll.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+80:[ 	]+230101ac[ 	]+sc.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+84:[ 	]+240101ac[ 	]+ldptr.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+88:[ 	]+250101ac[ 	]+stptr.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+8c:[ 	]+284401ac[ 	]+ld.h[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+90:[ 	]+288401ac[ 	]+ld.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+94:[ 	]+290401ac[ 	]+st.b[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+98:[ 	]+294401ac[ 	]+st.h[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+9c:[ 	]+298401ac[ 	]+st.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+a0:[ 	]+2a0401ac[ 	]+ld.bu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+a4:[ 	]+2a4401ac[ 	]+ld.hu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+a8:[ 	]+2a8401ac[ 	]+ld.wu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+ac:[ 	]+2ac401a2[ 	]+preld[ 	]+0x2,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+b0:[ 	]+382c39a2[ 	]+preldx[ 	]+0x2,[ 	]+\$t1,[ 	]+\$t2
+[ 	]+b4:[ 	]+2b048d8a[ 	]+fld.s[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+b8:[ 	]+2b448d8a[ 	]+fst.s[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291\(0x123\)
+diff --git a/gas/testsuite/gas/loongarch/imm_ins_32.s b/gas/testsuite/gas/loongarch/imm_ins_32.s
+new file mode 100644
+index 00000000..e105548e
+--- /dev/null
+++ b/gas/testsuite/gas/loongarch/imm_ins_32.s
+@@ -0,0 +1,60 @@
+.equ a, 0x123
+.equ d, 2
+.equ e,0x100
+
+li.w $r12, a
+
+alsl.w $r11,$r12,$r13,d
+alsl.wu $r11,$r12,$r13,d
+bytepick.w $r11,$r12,$r13,d
+
+break d
+dbcl d
+syscall d
+
+slli.w $r11,$r12,d
+srli.w $r11,$r12,d
+srai.w $r12,$r13,d
+
+bstrins.w $r12,$r13,d,d
+
+slti $r12,$r13,a
+sltui $r12,$r13,a
+addi.w $r12,$r13,a
+andi $r12,$r13,d
+ori  $r12,$r13,d
+xori $r12,$r13,d
+lu12i.w $r12,a
+pcaddi $r12,a
+pcalau12i $r12,a
+pcaddu12i $r12,a
+pcaddu18i $r12,a
+
+csrrd $r12,a
+csrwr $r12,a
+csrxchg $r12,$r13,d
+cacop d,$r13,d
+lddir $r12,$r13,d
+ldpte $r12,d
+
+invtlb d,$r13,$r14
+
+ll.w $r12,$r13,e
+sc.w $r12,$r13,e
+ll.d $r12,$r13,e
+sc.d $r12,$r13,e
+ldptr.w $r12,$r13,e
+stptr.w $r12,$r13,e
+ld.h $r12,$r13,e
+ld.w $r12,$r13,e
+st.b $r12,$r13,e
+st.h $r12,$r13,e
+st.w $r12,$r13,e
+ld.bu $r12,$r13,e
+ld.hu $r12,$r13,e
+ld.wu $r12,$r13,e
+preld d,$r13,e
+preldx d,$r13,$r14
+
+fld.s $f10,$r12,a
+fst.s $f10,$r12,a
+diff --git a/gas/testsuite/gas/loongarch/imm_ins_label-fail.d b/gas/testsuite/gas/loongarch/imm_ins_label-fail.d
+new file mode 100644
+index 00000000..4301a007
+--- /dev/null
+++ b/gas/testsuite/gas/loongarch/imm_ins_label-fail.d
+@@ -0,0 +1,3 @@
+#as:
+#source: imm_ins_label-fail.s
+#error_output: imm_ins_label-fail.l
+diff --git a/gas/testsuite/gas/loongarch/imm_ins_label-fail.l b/gas/testsuite/gas/loongarch/imm_ins_label-fail.l
+new file mode 100644
+index 00000000..e0fec2fe
+--- /dev/null
+++ b/gas/testsuite/gas/loongarch/imm_ins_label-fail.l
+@@ -0,0 +1,3 @@
+.*Assembler messages:
+.*Error: illegal operand: Label
+.*Error: illegal operand: Label
+diff --git a/gas/testsuite/gas/loongarch/imm_ins_label-fail.s b/gas/testsuite/gas/loongarch/imm_ins_label-fail.s
+new file mode 100644
+index 00000000..84b2d192
+--- /dev/null
+++ b/gas/testsuite/gas/loongarch/imm_ins_label-fail.s
+@@ -0,0 +1,3 @@
+Label:
+    li.w $r12, Label
+    addi.w $r12, $r13, Label
+diff --git a/gas/testsuite/gas/loongarch/li.d b/gas/testsuite/gas/loongarch/li.d
+new file mode 100644
+index 00000000..850a3f48
+--- /dev/null
+++ b/gas/testsuite/gas/loongarch/li.d
+@@ -0,0 +1,21 @@
+#as:
+#objdump: -dr
+#skip: loongarch32-*-*
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+00000000.* <_start>:
+[ 	]+0:[ 	]+03803c06[ 	]+ori[ 	]+\$a2,[ 	]+\$zero,[ 	]+0xf
+[ 	]+4:[ 	]+1a000005[ 	]+pcalau12i[ 	]+\$a1,[ 	]+0
+[ 	]+4:[ 	]+R_LARCH_PCALA_HI20[ 	]+.rodata
+[ 	]+8:[ 	]+02c000a5[ 	]+addi.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
+[ 	]+8:[ 	]+R_LARCH_PCALA_LO12[ 	]+.rodata
+[ 	]+c:[ 	]+03800404[ 	]+ori[ 	]+\$a0,[ 	]+\$zero,[ 	]+0x1
+[ 	]+10:[ 	]+0381000b[ 	]+ori[ 	]+\$a7,[ 	]+\$zero,[ 	]+0x40
+[ 	]+14:[ 	]+002b0000[ 	]+syscall[ 	]+0x0
+[ 	]+18:[ 	]+00150004[ 	]+move[ 	]+\$a0,[ 	]+\$zero
+[ 	]+1c:[ 	]+0381740b[ 	]+ori[ 	]+\$a7,[ 	]+\$zero,[ 	]+0x5d
+[ 	]+20:[ 	]+002b0000[ 	]+syscall[ 	]+0x0
+diff --git a/gas/testsuite/gas/loongarch/li.s b/gas/testsuite/gas/loongarch/li.s
+new file mode 100644
+index 00000000..e95a527f
+--- /dev/null
+++ b/gas/testsuite/gas/loongarch/li.s
+@@ -0,0 +1,22 @@
+.equ EXIT_SUCCESS, 0
+.equ STDOUT, 1
+.equ SYS_exit, 93
+.equ SYS_write, 64
+
+.section .rodata
+msg:
+    .string "hello, world!\n"
+    len = . - msg
+
+.text
+    .globl  _start
+_start:
+    li.w        $a2, len
+    la.local    $a1, msg
+    li.w        $a0, STDOUT
+    li.w        $a7, SYS_write
+    syscall     0x0
+
+    li.w        $a0, EXIT_SUCCESS
+    li.w        $a7, SYS_exit
+    syscall     0x0
+-- 
+2.27.0
+
--- a/SME-0001-aarch64-SME-Add-sme-option-to-march.patch
+++ b/SME-0001-aarch64-SME-Add-sme-option-to-march.patch
@ -0,0 +1,139 @@
+From 90774538ff7755dcc12d997d52b76a484b8c68d2 Mon Sep 17 00:00:00 2001
+From: Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+Date: Wed, 17 Nov 2021 19:02:54 +0000
+Subject: [PATCH 01/10] aarch64: [SME] Add +sme option to -march
+
+Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=57f02370a1e55bf09d3ede5ba6b2fcc78b40200a
+
+This series of patches (tagged [SME]) add support for the Scalable
+Matrix Extension. Patch introduces new command line options: +sme, +sme-f64 and
+sme-i64 to -march command line options.
+
+gas/ChangeLog:
+
+	* NEWS: Updated docs.
+	* config/tc-aarch64.c: New SME command line options.
+	* doc/c-aarch64.texi: Update docs.
+
+include/ChangeLog:
+
+	* opcode/aarch64.h (AARCH64_FEATURE_SME): New flag.
+	(AARCH64_FEATURE_SME_F64): New flag.
+	(AARCH64_FEATURE_SME_I64): New flag.
+
+opcodes/ChangeLog:
+
+	* aarch64-tbl.h (SME): New feature object.
+---
+ gas/NEWS                 |  2 ++
+ gas/config/tc-aarch64.c  | 11 +++++++++++
+ gas/doc/c-aarch64.texi   |  6 ++++++
+ include/opcode/aarch64.h |  3 +++
+ opcodes/aarch64-tbl.h    | 11 +++++++++++
+ 5 files changed, 33 insertions(+)
+
+diff --git a/gas/NEWS b/gas/NEWS
+index 9e24e4dd..0c5db3bf 100644
+--- a/gas/NEWS
+++ b/gas/NEWS
+@@ -2,6 +2,8 @@
+ 
+ * Add support for Intel AVX512_FP16 instructions.
+ 
+* Add support for Scalable Matrix Extension (SME) for AArch64.
+
+ Changes in 2.37:
+ 
+ * arm-symbianelf support removed.
+diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
+index 2eaad63a..f750fad4 100644
+--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
+@@ -9273,6 +9273,17 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
+ 					 | AARCH64_FEATURE_SHA3, 0)},
+   {"sve2-bitperm",	AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM, 0),
+ 			AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0)},
+  {"sme",		AARCH64_FEATURE (AARCH64_FEATURE_SME, 0),
+			AARCH64_FEATURE (AARCH64_FEATURE_SVE2
+					 | AARCH64_FEATURE_BFLOAT16, 0)},
+  {"sme-f64",		AARCH64_FEATURE (AARCH64_FEATURE_SME_F64, 0),
+			AARCH64_FEATURE (AARCH64_FEATURE_SME
+					 | AARCH64_FEATURE_SVE2
+					 | AARCH64_FEATURE_BFLOAT16, 0)},
+  {"sme-i64",		AARCH64_FEATURE (AARCH64_FEATURE_SME_I64, 0),
+			AARCH64_FEATURE (AARCH64_FEATURE_SME
+					 | AARCH64_FEATURE_SVE2
+					 | AARCH64_FEATURE_BFLOAT16, 0)},
+   {"bf16",		AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0),
+ 			AARCH64_ARCH_NONE},
+   {"i8mm",		AARCH64_FEATURE (AARCH64_FEATURE_I8MM, 0),
+diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
+index 79dce2f7..1bd93821 100644
+--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
+@@ -210,6 +210,12 @@ automatically cause those extensions to be disabled.
+  @tab Enable the Execution and Data and Prediction instructions.
+ @item @code{rng} @tab ARMv8.5-A @tab No
+  @tab Enable ARMv8.5-A random number instructions.
+@item @code{sme} @tab Armv9-A @tab No
+ @tab Enable SME Extension.
+@item @code{sme-f64} @tab Armv9-A @tab No
+ @tab Enable SME F64 Extension.
+@item @code{sme-i64} @tab Armv9-A @tab No
+ @tab Enable SME I64 Extension.
+ @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
+  @tab Enable Speculative Store Bypassing Safe state read and write.
+ @item @code{memtag} @tab ARMv8.5-A @tab No
+diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
+index 2bbd593c..7256028d 100644
+--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
+@@ -51,6 +51,7 @@ typedef uint32_t aarch64_insn;
+ #define AARCH64_FEATURE_V8_4	     (1ULL << 11) /* ARMv8.4 processors.  */
+ #define AARCH64_FEATURE_V8_R	     (1ULL << 12) /* Armv8-R processors.  */
+ #define AARCH64_FEATURE_V8_7	     (1ULL << 13) /* Armv8.7 processors.  */
+#define AARCH64_FEATURE_SME	     (1ULL << 14) /* Scalable Matrix Extension.  */
+ #define AARCH64_FEATURE_LS64	     (1ULL << 15) /* Atomic 64-byte load/store.  */
+ #define AARCH64_FEATURE_PAC	     (1ULL << 16) /* v8.3 Pointer Authentication.  */
+ #define AARCH64_FEATURE_FP	     (1ULL << 17) /* FP instructions.  */
+@@ -90,6 +91,8 @@ typedef uint32_t aarch64_insn;
+ #define AARCH64_FEATURE_F32MM	     (1ULL << 53)
+ #define AARCH64_FEATURE_F64MM	     (1ULL << 54)
+ #define AARCH64_FEATURE_FLAGM	     (1ULL << 55) /* v8.4 Flag Manipulation.  */
+#define AARCH64_FEATURE_SME_F64	     (1ULL << 57) /* SME F64.  */
+#define AARCH64_FEATURE_SME_I64	     (1ULL << 58) /* SME I64.  */
+ 
+ /* Crypto instructions are the combination of AES and SHA2.  */
+ #define AARCH64_FEATURE_CRYPTO	(AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
+diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
+index 17ea851c..d63b0810 100644
+--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
+@@ -2401,6 +2401,14 @@ static const aarch64_feature_set aarch64_feature_sve2sm4 =
+   AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SM4, 0);
+ static const aarch64_feature_set aarch64_feature_sve2bitperm =
+   AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_BITPERM, 0);
+static const aarch64_feature_set aarch64_feature_sme =
+  AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME, 0);
+static const aarch64_feature_set aarch64_feature_sme_f64 =
+  AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME
+       | AARCH64_FEATURE_SME_F64, 0);
+static const aarch64_feature_set aarch64_feature_sme_i64 =
+  AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME
+       | AARCH64_FEATURE_SME_I64, 0);
+ static const aarch64_feature_set aarch64_feature_v8_6 =
+   AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0);
+ static const aarch64_feature_set aarch64_feature_v8_7 =
+@@ -2458,6 +2466,9 @@ static const aarch64_feature_set aarch64_feature_flagm =
+ #define SVE2_SHA3	&aarch64_feature_sve2sha3
+ #define SVE2_SM4		&aarch64_feature_sve2sm4
+ #define SVE2_BITPERM	&aarch64_feature_sve2bitperm
+#define SME		&aarch64_feature_sme
+#define SME_F64		&aarch64_feature_sme_f64
+#define SME_I64		&aarch64_feature_sme_i64
+ #define ARMV8_6		&aarch64_feature_v8_6
+ #define ARMV8_6_SVE		&aarch64_feature_v8_6
+ #define BFLOAT16_SVE	&aarch64_feature_bfloat16_sve
+-- 
+2.19.1
+
--- a/SME-0002-aarch64-SME-Add-SME-instructions.patch
+++ b/SME-0002-aarch64-SME-Add-SME-instructions.patch
--- a/SME-0003-aarch64-SME-Add-MOV-and-MOVA-instructions.patch
+++ b/SME-0003-aarch64-SME-Add-MOV-and-MOVA-instructions.patch
--- a/SME-0004-aarch64-SME-Add-ZERO-instruction.patch
+++ b/SME-0004-aarch64-SME-Add-ZERO-instruction.patch
--- a/SME-0005-aarch64-SME-Add-LD1x-ST1x-LDR-and-STR-instructions.patch
+++ b/SME-0005-aarch64-SME-Add-LD1x-ST1x-LDR-and-STR-instructions.patch
--- a/SME-0006-aarch64-SME-Add-SME-mode-selection-and-state-access-.patch
+++ b/SME-0006-aarch64-SME-Add-SME-mode-selection-and-state-access-.patch
--- a/SME-0007-aarch64-SME-Add-new-SME-system-registers.patch
+++ b/SME-0007-aarch64-SME-Add-new-SME-system-registers.patch
@ -0,0 +1,153 @@
+From dd79dd44a7e7ebc7533cfdb60f94fe2a4657ce27 Mon Sep 17 00:00:00 2001
+From: Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+Date: Wed, 17 Nov 2021 20:20:50 +0000
+Subject: [PATCH 07/10] aarch64: [SME] Add new SME system registers
+
+Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8f1bfdb44894423680a6d56a0994dafb4b82efca
+
+This patch is adding miscellaneous SME related system registers.
+
+gas/ChangeLog:
+
+	* testsuite/gas/aarch64/sme-sysreg.d: New test.
+	* testsuite/gas/aarch64/sme-sysreg.s: New test.
+	* testsuite/gas/aarch64/sme-sysreg-illegal.d: New test.
+	* testsuite/gas/aarch64/sme-sysreg-illegal.l: New test.
+	* testsuite/gas/aarch64/sme-sysreg-illegal.s: New test.
+
+opcodes/ChangeLog:
+
+	* aarch64-opc.c: New system registers id_aa64smfr0_el1,
+	smcr_el1, smcr_el12, smcr_el2, smcr_el3, smpri_el1,
+	smprimap_el2, smidr_el1, tpidr2_el0 and mpamsm_el1.
+---
+ .../gas/aarch64/sme-sysreg-illegal.d          |  3 ++
+ .../gas/aarch64/sme-sysreg-illegal.l          |  3 ++
+ .../gas/aarch64/sme-sysreg-illegal.s          |  3 ++
+ gas/testsuite/gas/aarch64/sme-sysreg.d        | 29 +++++++++++++++++++
+ gas/testsuite/gas/aarch64/sme-sysreg.s        | 23 +++++++++++++++
+ opcodes/aarch64-opc.c                         | 12 +++++++-
+ 6 files changed, 72 insertions(+), 1 deletion(-)
+ create mode 100644 gas/testsuite/gas/aarch64/sme-sysreg-illegal.d
+ create mode 100644 gas/testsuite/gas/aarch64/sme-sysreg-illegal.l
+ create mode 100644 gas/testsuite/gas/aarch64/sme-sysreg-illegal.s
+ create mode 100644 gas/testsuite/gas/aarch64/sme-sysreg.d
+ create mode 100644 gas/testsuite/gas/aarch64/sme-sysreg.s
+
+diff --git a/gas/testsuite/gas/aarch64/sme-sysreg-illegal.d b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.d
+new file mode 100644
+index 00000000..ff0e855f
+--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.d
+@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sme-sysreg-illegal.s
+#warning_output: sme-sysreg-illegal.l
+diff --git a/gas/testsuite/gas/aarch64/sme-sysreg-illegal.l b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.l
+new file mode 100644
+index 00000000..6baad135
+--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.l
+@@ -0,0 +1,3 @@
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Warning: specified register cannot be written to at operand 1 -- `msr id_aa64smfr0_el1,x0'
+[^:]*:[0-9]+: Warning: specified register cannot be written to at operand 1 -- `msr smidr_el1,x0'
+diff --git a/gas/testsuite/gas/aarch64/sme-sysreg-illegal.s b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.s
+new file mode 100644
+index 00000000..057a6bf0
+--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.s
+@@ -0,0 +1,3 @@
+/* Write to r/o SME system registers.  */
+msr id_aa64smfr0_el1, x0
+msr smidr_el1, x0
+diff --git a/gas/testsuite/gas/aarch64/sme-sysreg.d b/gas/testsuite/gas/aarch64/sme-sysreg.d
+new file mode 100644
+index 00000000..8eaf73ca
+--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-sysreg.d
+@@ -0,0 +1,29 @@
+#name: SME extension (system registers)
+#as: -march=armv8-a+sme
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+   0:	d53b4240 	mrs	x0, svcr
+   4:	d53804a0 	mrs	x0, id_aa64smfr0_el1
+   8:	d53812c0 	mrs	x0, smcr_el1
+   c:	d53d12c0 	mrs	x0, smcr_el12
+  10:	d53c12c0 	mrs	x0, smcr_el2
+  14:	d53e12c0 	mrs	x0, smcr_el3
+  18:	d5381280 	mrs	x0, smpri_el1
+  1c:	d53c12a0 	mrs	x0, smprimap_el2
+  20:	d53900c0 	mrs	x0, smidr_el1
+  24:	d53bd0a0 	mrs	x0, tpidr2_el0
+  28:	d538a560 	mrs	x0, mpamsm_el1
+  2c:	d51b4240 	msr	svcr, x0
+  30:	d51812c0 	msr	smcr_el1, x0
+  34:	d51d12c0 	msr	smcr_el12, x0
+  38:	d51c12c0 	msr	smcr_el2, x0
+  3c:	d51e12c0 	msr	smcr_el3, x0
+  40:	d5181280 	msr	smpri_el1, x0
+  44:	d51c12a0 	msr	smprimap_el2, x0
+  48:	d51bd0a0 	msr	tpidr2_el0, x0
+  4c:	d518a560 	msr	mpamsm_el1, x0
+diff --git a/gas/testsuite/gas/aarch64/sme-sysreg.s b/gas/testsuite/gas/aarch64/sme-sysreg.s
+new file mode 100644
+index 00000000..ce8a2942
+--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-sysreg.s
+@@ -0,0 +1,23 @@
+/* Read SME system registers.  */
+mrs x0, svcr
+mrs x0, id_aa64smfr0_el1
+mrs x0, smcr_el1
+mrs x0, smcr_el12
+mrs x0, smcr_el2
+mrs x0, smcr_el3
+mrs x0, smpri_el1
+mrs x0, smprimap_el2
+mrs x0, smidr_el1
+mrs x0, tpidr2_el0
+mrs x0, mpamsm_el1
+
+/* Write to SME system registers.  */
+msr svcr, x0
+msr smcr_el1, x0
+msr smcr_el12, x0
+msr smcr_el2, x0
+msr smcr_el3, x0
+msr smpri_el1, x0
+msr smprimap_el2, x0
+msr tpidr2_el0, x0
+msr mpamsm_el1, x0
+diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
+index dba8bcba..923ddefe 100644
+--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
+@@ -4826,7 +4826,17 @@ const aarch64_sys_reg aarch64_sys_regs [] =
+   SR_CORE ("gpccr_el3",     CPENC (3,6,C2,C1,6), 0),
+   SR_CORE ("gptbr_el3",     CPENC (3,6,C2,C1,4), 0),
+ 
+-  SR_SME ("svcr",           CPENC (3,3,C4,C2,2), 0),
+  SR_SME ("svcr",             CPENC (3,3,C4,C2,2),  0),
+  SR_SME ("id_aa64smfr0_el1", CPENC (3,0,C0,C4,5),  F_REG_READ),
+  SR_SME ("smcr_el1",         CPENC (3,0,C1,C2,6),  0),
+  SR_SME ("smcr_el12",        CPENC (3,5,C1,C2,6),  0),
+  SR_SME ("smcr_el2",         CPENC (3,4,C1,C2,6),  0),
+  SR_SME ("smcr_el3",         CPENC (3,6,C1,C2,6),  0),
+  SR_SME ("smpri_el1",        CPENC (3,0,C1,C2,4),  0),
+  SR_SME ("smprimap_el2",     CPENC (3,4,C1,C2,5),  0),
+  SR_SME ("smidr_el1",        CPENC (3,1,C0,C0,6),  F_REG_READ),
+  SR_SME ("tpidr2_el0",       CPENC (3,3,C13,C0,5), 0),
+  SR_SME ("mpamsm_el1",       CPENC (3,0,C10,C5,3), 0),
+ 
+   { 0, CPENC (0,0,0,0,0), 0, 0 }
+ };
+-- 
+2.19.1
+
--- a/SME-0008-aarch64-SME-SVE2-instructions-added-to-support-SME.patch
+++ b/SME-0008-aarch64-SME-SVE2-instructions-added-to-support-SME.patch
--- a/SME-0009-aarch64-Check-for-register-aliases-before-mnemonics.patch
+++ b/SME-0009-aarch64-Check-for-register-aliases-before-mnemonics.patch
@ -0,0 +1,221 @@
+From e4afe464b120e181747b1108a23e0da2d16abd99 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 30 Nov 2021 17:50:24 +0000
+Subject: [PATCH 09/10] aarch64: Check for register aliases before mnemonics
+
+Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=2dd3146b4ffcb8528a6e093741ba31636afdf8ae
+
+Previously we would not accept:
+
+	A .req B
+
+if A happened to be the name of an instruction.  Adding new
+instructions could therefore invalidate existing register aliases.
+
+I noticed this with a test that used "zero" as a register alias
+for "xzr", where "zero" is now also the name of an SME instruction.
+I don't have any evidence that "real" code is doing this, but it
+seems at least plausible.
+
+This patch switches things so that we check for register aliases
+first.  It might slow down parsing slightly, but the difference
+is unlikely to be noticeable.
+
+Things like:
+
+	b	.req + 0
+
+still work, since create_register_alias checks for " .req ",
+and with the input scrubber, we'll only keep whitespace after
+.req if it's followed by another name.  If there's some valid
+expression that I haven't thought about that is scrubbed to
+" .req ", users could avoid the ambiguity by wrapping .req
+in parentheses.
+
+The new test for invalid aliases already passed.  I just wanted
+something to exercise the !dot condition.
+
+I can't find a way of exercising the (existing) p == base condition,
+but I'm not brave enough to say that it can never happen.  If it does
+happen, get_mnemonic_name would return an empty string.
+
+gas/
+	* config/tc-aarch64.c (opcode_lookup): Move mnemonic extraction
+	code to...
+	(md_assemble): ...here.  Check for register aliases first.
+	* testsuite/gas/aarch64/register_aliases.d,
+	testsuite/gas/aarch64/register_aliases.s: Test for a register
+	alias called "zero".
+	* testsuite/gas/aarch64/register_aliases_invalid.d,
+	testsuite/gas/aarch64/register_aliases_invalid.l,
+	testsuite/gas/aarch64/register_aliases_invalid.s: New test.
+---
+ gas/config/tc-aarch64.c                       | 62 +++++++++----------
+ gas/testsuite/gas/aarch64/register_aliases.d  |  1 +
+ gas/testsuite/gas/aarch64/register_aliases.s  |  3 +-
+ .../gas/aarch64/register_aliases_invalid.d    |  1 +
+ .../gas/aarch64/register_aliases_invalid.l    |  3 +
+ .../gas/aarch64/register_aliases_invalid.s    |  2 +
+ 6 files changed, 38 insertions(+), 34 deletions(-)
+ create mode 100644 gas/testsuite/gas/aarch64/register_aliases_invalid.d
+ create mode 100644 gas/testsuite/gas/aarch64/register_aliases_invalid.l
+ create mode 100644 gas/testsuite/gas/aarch64/register_aliases_invalid.s
+
+diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
+index ea58d9b0..c9677edc 100644
+--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
+@@ -5786,25 +5786,18 @@ lookup_mnemonic (const char *start, int len)
+ }
+ 
+ /* Subroutine of md_assemble, responsible for looking up the primary
+-   opcode from the mnemonic the user wrote.  STR points to the
+-   beginning of the mnemonic. */
+   opcode from the mnemonic the user wrote.  BASE points to the beginning
+   of the mnemonic, DOT points to the first '.' within the mnemonic
+   (if any) and END points to the end of the mnemonic.  */
+ 
+ static templates *
+-opcode_lookup (char **str)
+opcode_lookup (char *base, char *dot, char *end)
+ {
+-  char *end, *base, *dot;
+   const aarch64_cond *cond;
+   char condname[16];
+   int len;
+ 
+-  /* Scan up to the end of the mnemonic, which must end in white space,
+-     '.', or end of string.  */
+-  dot = 0;
+-  for (base = end = *str; is_part_of_name(*end); end++)
+-    if (*end == '.' && !dot)
+-      dot = end;
+-
+-  if (end == base || dot == base)
+  if (dot == end)
+     return 0;
+ 
+   inst.cond = COND_ALWAYS;
+@@ -5813,23 +5806,13 @@ opcode_lookup (char **str)
+   if (dot)
+     {
+       cond = str_hash_find_n (aarch64_cond_hsh, dot + 1, end - dot - 1);
+-      if (cond)
+-	{
+-	  inst.cond = cond->value;
+-	  *str = end;
+-	}
+-      else
+-	{
+-	  *str = dot;
+-	  return 0;
+-	}
+      if (!cond)
+	return 0;
+      inst.cond = cond->value;
+       len = dot - base;
+     }
+   else
+-    {
+-      *str = end;
+-      len = end - base;
+-    }
+    len = end - base;
+ 
+   if (inst.cond == COND_ALWAYS)
+     {
+@@ -7918,7 +7901,6 @@ dump_opcode_operands (const aarch64_opcode *opcode)
+ void
+ md_assemble (char *str)
+ {
+-  char *p = str;
+   templates *template;
+   const aarch64_opcode *opcode;
+   aarch64_inst *inst_base;
+@@ -7941,14 +7923,28 @@ md_assemble (char *str)
+   DEBUG_TRACE ("==============================");
+   DEBUG_TRACE ("Enter md_assemble with %s", str);
+ 
+-  template = opcode_lookup (&p);
+  /* Scan up to the end of the mnemonic, which must end in whitespace,
+     '.', or end of string.  */
+  char *p = str;
+  char *dot = 0;
+  for (; is_part_of_name (*p); p++)
+    if (*p == '.' && !dot)
+      dot = p;
+
+  if (p == str)
+    {
+      as_bad (_("unknown mnemonic -- `%s'"), str);
+      return;
+    }
+
+  if (!dot && create_register_alias (str, p))
+    return;
+
+  template = opcode_lookup (str, dot, p);
+   if (!template)
+     {
+-      /* It wasn't an instruction, but it might be a register alias of
+-         the form alias .req reg directive.  */
+-      if (!create_register_alias (str, p))
+-	as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str),
+-		str);
+      as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str),
+	      str);
+       return;
+     }
+ 
+diff --git a/gas/testsuite/gas/aarch64/register_aliases.d b/gas/testsuite/gas/aarch64/register_aliases.d
+index eab63870..8d614b47 100644
+--- a/gas/testsuite/gas/aarch64/register_aliases.d
+++ b/gas/testsuite/gas/aarch64/register_aliases.d
+@@ -10,3 +10,4 @@ Disassembly of section \.text:
+    8:	f94003b1 	ldr	x17, \[x29\]
+    c:	f90003b0 	str	x16, \[x29\]
+   10:	f94003b1 	ldr	x17, \[x29\]
+  14:	f900001f 	str	xzr, \[x0\]
+diff --git a/gas/testsuite/gas/aarch64/register_aliases.s b/gas/testsuite/gas/aarch64/register_aliases.s
+index fcd06507..856be569 100644
+--- a/gas/testsuite/gas/aarch64/register_aliases.s
+++ b/gas/testsuite/gas/aarch64/register_aliases.s
+@@ -3,9 +3,10 @@
+ 	fp 	.req 	x29
+ 	ip0	.req 	x16
+ 	ip1	.req 	x17
+	zero	.req	xzr
+ 	add	ip0, ip0, lr
+ 	str 	ip0, [fp]
+ 	ldr	ip1, [fp]
+ 	str 	IP0, [fp]
+ 	ldr	IP1, [fp]
+-
+	str	zero, [x0]
+diff --git a/gas/testsuite/gas/aarch64/register_aliases_invalid.d b/gas/testsuite/gas/aarch64/register_aliases_invalid.d
+new file mode 100644
+index 00000000..7c453ce0
+--- /dev/null
+++ b/gas/testsuite/gas/aarch64/register_aliases_invalid.d
+@@ -0,0 +1 @@
+#error_output: register_aliases_invalid.l
+diff --git a/gas/testsuite/gas/aarch64/register_aliases_invalid.l b/gas/testsuite/gas/aarch64/register_aliases_invalid.l
+new file mode 100644
+index 00000000..6350049d
+--- /dev/null
+++ b/gas/testsuite/gas/aarch64/register_aliases_invalid.l
+@@ -0,0 +1,3 @@
+.*:
+.*: Error: unknown mnemonic `lr\.req' -- `lr\.req x30'
+.*: Error: unknown mnemonic `lr\.a' -- `lr\.a .req x30'
+diff --git a/gas/testsuite/gas/aarch64/register_aliases_invalid.s b/gas/testsuite/gas/aarch64/register_aliases_invalid.s
+new file mode 100644
+index 00000000..2df2eaab
+--- /dev/null
+++ b/gas/testsuite/gas/aarch64/register_aliases_invalid.s
+@@ -0,0 +1,2 @@
+lr.req 	x30
+lr.a	.req	x30
+-- 
+2.19.1
+
--- a/SME-0010-aarch64-Add-support-for-new-SME-instructions.patch
+++ b/SME-0010-aarch64-Add-support-for-new-SME-instructions.patch
--- a/aarch64-add-l4-instruction.patch
+++ b/aarch64-add-l4-instruction.patch
@ -0,0 +1,60 @@
+From 0bd604ffdd24e40144db5e60ada7658645f9d276 Mon Sep 17 00:00:00 2001
+From: z00562913 <zhaoshujian@huawei.com>
+Date: Fri, 1 Mar 2024 09:58:23 +0800
+Subject: [PATCH] add llc L4 instrcution
+
+---
+ opcodes/aarch64-opc.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
+index dea4b8e6..00ebbb11 100644
+--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
+@@ -86,8 +86,8 @@ const char *const aarch64_sve_prfop_array[16] = {
+   "pldl2strm",
+   "pldl3keep",
+   "pldl3strm",
+-  0,
+-  0,
+  "pldl4keep", 
+  "pldl4strm", 
+   /* 8-15.  */
+   "pstl1keep",
+   "pstl1strm",
+@@ -95,8 +95,8 @@ const char *const aarch64_sve_prfop_array[16] = {
+   "pstl2strm",
+   "pstl3keep",
+   "pstl3strm",
+-  0,
+-  0
+  "pstl4keep", 
+  "pstl4strm" 
+ };
+ 
+ /* Helper functions to determine which operand to be used to encode/decode
+@@ -501,8 +501,8 @@ const struct aarch64_name_value_pair aarch64_prfops[32] =
+   { "pldl2strm", B(0, 2, 1) },
+   { "pldl3keep", B(0, 3, 0) },
+   { "pldl3strm", B(0, 3, 1) },
+-  { NULL, 0x06 },
+-  { NULL, 0x07 },
+  { "pldl4keep", B(0, 4, 0) }, 
+  { "pldl4strm", B(0, 4, 1) },
+   { "plil1keep", B(1, 1, 0) },
+   { "plil1strm", B(1, 1, 1) },
+   { "plil2keep", B(1, 2, 0) },
+@@ -517,8 +517,8 @@ const struct aarch64_name_value_pair aarch64_prfops[32] =
+   { "pstl2strm", B(2, 2, 1) },
+   { "pstl3keep", B(2, 3, 0) },
+   { "pstl3strm", B(2, 3, 1) },
+-  { NULL, 0x16 },
+-  { NULL, 0x17 },
+  { "pstl4keep", B(2, 4, 0) }, 
+  { "pstl4strm", B(2, 4, 1) }, 
+   { NULL, 0x18 },
+   { NULL, 0x19 },
+   { NULL, 0x1a },
+-- 
+2.33.0
+
--- a/backport-CVE-2019-1010204.patch
+++ b/backport-CVE-2019-1010204.patch
--- a/backport-CVE-2022-38533.patch
+++ b/backport-CVE-2022-38533.patch
@ -0,0 +1,33 @@
+From ef186fe54aa6d281a3ff8a9528417e5cc614c797 Mon Sep 17 00:00:00 2001
+From: Alan Modra <amodra@gmail.com>
+Date: Sat, 13 Aug 2022 15:32:47 +0930
+Subject: [PATCH] PR29482 - strip: heap-buffer-overflow
+
+	PR 29482
+	* coffcode.h (coff_set_section_contents): Sanity check _LIB.
+---
+ bfd/coffcode.h | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/bfd/coffcode.h b/bfd/coffcode.h
+index 67aaf158ca1..52027981c3f 100644
+--- a/bfd/coffcode.h
+++ b/bfd/coffcode.h
+@@ -4302,10 +4302,13 @@ coff_set_section_contents (bfd * abfd,
+ 
+ 	rec = (bfd_byte *) location;
+ 	recend = rec + count;
+-	while (rec < recend)
+	while (recend - rec >= 4)
+ 	  {
+	    size_t len = bfd_get_32 (abfd, rec);
+	    if (len == 0 || len > (size_t) (recend - rec) / 4)
+	      break;
+	    rec += len * 4;
+ 	    ++section->lma;
+-	    rec += bfd_get_32 (abfd, rec) * 4;
+ 	  }
+ 
+ 	BFD_ASSERT (rec == recend);
+-- 
+2.39.3
--- a/backport-CVE-2022-47008.patch
+++ b/backport-CVE-2022-47008.patch
--- a/backport-Fix-a-potential-use-of-an-uninitialised-value-in-the.patch
+++ b/backport-Fix-a-potential-use-of-an-uninitialised-value-in-the.patch
--- a/backport-0001-PR28391-strip-objcopy-preserve-dates-.a-cannot-set-t.patch
+++ b/backport-0001-PR28391-strip-objcopy-preserve-dates-.a-cannot-set-t.patch
--- a/backport-bfd-Close-the-file-descriptor-if-there-is-no-archive.patch
+++ b/backport-bfd-Close-the-file-descriptor-if-there-is-no-archive.patch
--- a/backport-binutils-AArch64-EFI.patch
+++ b/backport-binutils-AArch64-EFI.patch
--- a/backport-0001-texi2pod.pl-add-no-op-no-split-option-support-PR2814.patch
+++ b/backport-0001-texi2pod.pl-add-no-op-no-split-option-support-PR2814.patch
--- a/binutils.spec
+++ b/binutils.spec
@ -1,94 +1,130 @@
 Summary: Binary utilities
 Name:    binutils
 Version: 2.37
-Release: 23
+Release: 28
 License: GPLv3+
 URL:     https://sourceware.org/binutils

 Source:  https://ftp.gnu.org/gnu/binutils/binutils-%{version}.tar.xz

-# risc-v do not support gold linker.
-%ifnarch riscv64
+# risc-v loongarch64 do not support gold linker.
+%ifnarch riscv64 loongarch64
 %bcond_without gold
 %else
 %bcond_with gold
 %endif

-Patch0:  binutils-2.20.51.0.2-libtool-lib64.patch
-Patch1:  export-demangle.h-in-devel-package.patch
-#BUZ:845084
-Patch2:  binutils-2.22.52.0.4-no-config-h-check.patch
-#BUG:1452111
-Patch3:  binutils-2.27-aarch64-ifunc.patch
+# OpenEuler Patch Naming Rules
+# https://gitee.com/openeuler/TC/blob/master/oEEP/oEEP-0012%20openEuler%E8%BD%AF%E4%BB%B6%E5%8C%85%E9%9D%9Eupstream%E6%94%AF%E6%8C%81%E5%A4%9A%E6%9E%B6%E6%9E%84%E4%BB%A3%E7%A0%81%E6%8F%90%E4%BA%A4%E8%A7%84%E5%88%99.md

-#PATCH-CVE-UPSTREAM
-Patch4:  CVE-2019-1010204.patch
+# Patch 3000 - 4999

-Patch5:  Fix-a-potential-use-of-an-uninitialised-value-in-the.patch
-Patch6:  backport-CVE-2021-45078.patch
-Patch7:  backport-0001-CVE-2021-42574.patch
-Patch8:  backport-0002-CVE-2021-42574.patch
-Patch9:  backport-0003-CVE-2021-42574.patch
-Patch10: bfd-Close-the-file-descriptor-if-there-is-no-archive.patch
-Patch11: binutils-AArch64-EFI.patch
-Patch12: backport-0001-PR28391-strip-objcopy-preserve-dates-.a-cannot-set-t.patch
+Patch3001: backport-CVE-2019-1010204.patch
+Patch3002: backport-Fix-a-potential-use-of-an-uninitialised-value-in-the.patch
+Patch3003: backport-CVE-2021-45078.patch
+Patch3004: backport-0001-CVE-2021-42574.patch
+Patch3005: backport-0002-CVE-2021-42574.patch
+Patch3006: backport-0003-CVE-2021-42574.patch
+Patch3007: backport-bfd-Close-the-file-descriptor-if-there-is-no-archive.patch
+Patch3008: backport-binutils-AArch64-EFI.patch
+Patch3009: backport-PR28391-strip-objcopy-preserve-dates-.a-cannot-set-t.patch

-Patch13: 0001-x86-Add-int1-as-one-byte-opcode-0xf1.patch
-Patch14: 0002-x86-drop-OP_Mask.patch
-Patch15: 0003-x86-correct-VCVT-U-SI2SD-rounding-mode-handling.patch
-Patch16: 0004-x86-64-generalize-OP_G-s-EVEX.R-handling.patch
-Patch17: 0005-x86-64-properly-bounds-check-bnd-N-in-OP_G.patch
-Patch18: 0006-x86-fold-duplicate-register-printing-code.patch
-Patch19: 0007-x86-fold-duplicate-code-in-MOVSXD_Fixup.patch
-Patch20: 0008-x86-correct-EVEX.V-handling-outside-of-64-bit-mode.patch
-Patch21: 0009-x86-drop-vex_mode-and-vex_scalar_mode.patch
-Patch22: 0010-x86-fold-duplicate-vector-register-printing-code.patch
-Patch23: 0011-x86-drop-xmm_m-b-w-d-q-_mode.patch
-Patch24: 0012-x86-drop-vex_scalar_w_dq_mode.patch
-Patch25: 0013-x86-drop-dq-b-d-_mode.patch
-Patch26: 0014-x86-express-unduly-set-rounding-control-bits-in-disa.patch
-Patch27: 0015-x86-Simplify-check-for-distinct-TMM-register-operand.patch
-Patch28: 0016-PATCH-1-2-Enable-Intel-AVX512_FP16-instructions.patch
-Patch29: 0017-PATCH-2-2-Add-tests-for-Intel-AVX512_FP16-instructio.patch
-Patch30: 0018-x86-ELF-fix-.tfloat-output.patch
-Patch31: 0019-x86-ELF-fix-.ds.x-output.patch
-Patch32: 0020-x86-ELF-fix-.tfloat-output-with-hex-input.patch
-Patch33: 0021-x86-introduce-.hfloat-directive.patch
-Patch34: 0022-x86-Avoid-abort-on-invalid-broadcast.patch
-Patch35: 0023-x86-Put-back-3-aborts-in-OP_E_memory.patch
-Patch36: 0024-x86-Print-bad-on-invalid-broadcast-in-OP_E_memory.patch
-Patch37: 0025-x86-Terminate-mnemonicendp-in-swap_operand.patch
-Patch38: 0026-opcodes-Make-i386-dis.c-thread-safe.patch
-Patch39: 0027-x86-reduce-AVX512-FP16-set-of-insns-decoded-through-.patch
-Patch40: 0028-x86-reduce-AVX512-FP-set-of-insns-decoded-through-ve.patch
-Patch41: 0029-x86-consistently-use-scalar_mode-for-AVX512-FP16-sca.patch
-Patch42: backport-CVE-2022-38126.patch
+# AVX512
+Patch3010: AVX512-0001-x86-Add-int1-as-one-byte-opcode-0xf1.patch
+Patch3011: AVX512-0002-x86-drop-OP_Mask.patch
+Patch3012: AVX512-0003-x86-correct-VCVT-U-SI2SD-rounding-mode-handling.patch
+Patch3013: AVX512-0004-x86-64-generalize-OP_G-s-EVEX.R-handling.patch
+Patch3014: AVX512-0005-x86-64-properly-bounds-check-bnd-N-in-OP_G.patch
+Patch3015: AVX512-0006-x86-fold-duplicate-register-printing-code.patch
+Patch3016: AVX512-0007-x86-fold-duplicate-code-in-MOVSXD_Fixup.patch
+Patch3017: AVX512-0008-x86-correct-EVEX.V-handling-outside-of-64-bit-mode.patch
+Patch3018: AVX512-0009-x86-drop-vex_mode-and-vex_scalar_mode.patch
+Patch3019: AVX512-0010-x86-fold-duplicate-vector-register-printing-code.patch
+Patch3020: AVX512-0011-x86-drop-xmm_m-b-w-d-q-_mode.patch
+Patch3021: AVX512-0012-x86-drop-vex_scalar_w_dq_mode.patch
+Patch3022: AVX512-0013-x86-drop-dq-b-d-_mode.patch
+Patch3023: AVX512-0014-x86-express-unduly-set-rounding-control-bits-in-disa.patch
+Patch3024: AVX512-0015-x86-Simplify-check-for-distinct-TMM-register-operand.patch
+Patch3025: AVX512-0016-PATCH-1-2-Enable-Intel-AVX512_FP16-instructions.patch
+Patch3026: AVX512-0017-PATCH-2-2-Add-tests-for-Intel-AVX512_FP16-instructio.patch
+Patch3027: AVX512-0018-x86-ELF-fix-.tfloat-output.patch
+Patch3028: AVX512-0019-x86-ELF-fix-.ds.x-output.patch
+Patch3029: AVX512-0020-x86-ELF-fix-.tfloat-output-with-hex-input.patch
+Patch3030: AVX512-0021-x86-introduce-.hfloat-directive.patch
+Patch3031: AVX512-0022-x86-Avoid-abort-on-invalid-broadcast.patch
+Patch3032: AVX512-0023-x86-Put-back-3-aborts-in-OP_E_memory.patch
+Patch3033: AVX512-0024-x86-Print-bad-on-invalid-broadcast-in-OP_E_memory.patch
+Patch3034: AVX512-0025-x86-Terminate-mnemonicendp-in-swap_operand.patch
+Patch3035: AVX512-0026-opcodes-Make-i386-dis.c-thread-safe.patch
+Patch3036: AVX512-0027-x86-reduce-AVX512-FP16-set-of-insns-decoded-through-.patch
+Patch3037: AVX512-0028-x86-reduce-AVX512-FP-set-of-insns-decoded-through-ve.patch
+Patch3038: AVX512-0029-x86-consistently-use-scalar_mode-for-AVX512-FP16-sca.patch

-Patch43: backport-0001-texi2pod.pl-add-no-op-no-split-option-support-PR2814.patch
+Patch3039: backport-CVE-2022-38126.patch
+Patch3040: backport-texi2pod.pl-add-no-op-no-split-option-support-PR2814.patch
+Patch3041: backport-AArch64-Add-support-for-AArch64-EFI-efi-aarch64.patch
+Patch3042: backport-Add-support-for-AArch64-EFI-efi-aarch64.patch
+Patch3043: backport-don-t-over-align-file-positions-of-PE-executable-sec.patch
+Patch3044: backport-PR28186-SEGV-elf.c-7991-30-in-_bfd_elf_fixup_group_sections.patch
+Patch3045: backport-PR28422-build_id-use-after-free.patch
+Patch3046: backport-PR28540-segmentation-fault-on-NULL-byte_get.patch
+Patch3047: backport-CVE-2022-47008.patch
+Patch3048: backport-CVE-2022-47011.patch
+Patch3049: backport-CVE-2022-47696.patch
+Patch3050: backport-CVE-2021-46174.patch
+Patch3051: backport-CVE-2023-1972.patch
+Patch3052: backport-CVE-2022-48064.patch
+Patch3053: backport-CVE-2022-4285.patch
+Patch3054: backport-CVE-2022-38533.patch
+
+# SME
+Patch3055: SME-0001-aarch64-SME-Add-sme-option-to-march.patch
+Patch3056: SME-0002-aarch64-SME-Add-SME-instructions.patch
+Patch3057: SME-0003-aarch64-SME-Add-MOV-and-MOVA-instructions.patch
+Patch3058: SME-0004-aarch64-SME-Add-ZERO-instruction.patch
+Patch3059: SME-0005-aarch64-SME-Add-LD1x-ST1x-LDR-and-STR-instructions.patch
+Patch3060: SME-0006-aarch64-SME-Add-SME-mode-selection-and-state-access-.patch
+Patch3061: SME-0007-aarch64-SME-Add-new-SME-system-registers.patch
+Patch3062: SME-0008-aarch64-SME-SVE2-instructions-added-to-support-SME.patch
+Patch3063: SME-0009-aarch64-Check-for-register-aliases-before-mnemonics.patch
+Patch3064: SME-0010-aarch64-Add-support-for-new-SME-instructions.patch
+
+%ifarch loongarch64
+# LoongArch
+Patch4001: LoongArch-binutils-Add-LoongArch-support.patch
+Patch4002: LoongArch-Fixup-unresolve-symbols-problem.patch
+Patch4003: LoongArch-Fix-PLT-entry-generate-bug.patch
+Patch4004: LoongArch-gas-add-support-using-constant-variable-in.patch
+Patch4005: LoongArch-Fixup-gas-check-illegal-for-b-label.patch
+Patch4006: LoongArch-Fixup-check-file-for-ifunc-reloc.patch
+%endif
+
+# Patch 5000 -
+
+Patch5001: binutils-2.20.51.0.2-libtool-lib64.patch
+Patch5002: export-demangle.h-in-devel-package.patch
+# BUZ:845084
+Patch5003: binutils-2.22.52.0.4-no-config-h-check.patch
+# BUG:1452111
+Patch5004: binutils-2.27-aarch64-ifunc.patch
+Patch5005: Fix-gold-relocation-offset-and-adrp-signed-shife.patch
+Patch5006: aarch64-add-l4-instruction.patch
+
+%ifarch sw_64
+# sw_64
+Patch6001: sw_64-support-not-upstream-new-files.patch
+Patch6002: sw_64-support-not-upstream-modified-files.patch
+%endif

-Patch44: backport-AArch64-Add-support-for-AArch64-EFI-efi-aarch64.patch
-Patch45: backport-Add-support-for-AArch64-EFI-efi-aarch64.patch
-Patch46: backport-don-t-over-align-file-positions-of-PE-executable-sec.patch
-Patch47: backport-PR28186-SEGV-elf.c-7991-30-in-_bfd_elf_fixup_group_sections.patch
-Patch48: backport-PR28422-build_id-use-after-free.patch
-Patch49: backport-PR28540-segmentation-fault-on-NULL-byte_get.patch
-Patch50: Fix-gold-relocation-offset-and-adrp-signed-shife.patch
-Patch51: CVE-2022-47008.patch
-Patch52: backport-CVE-2022-47011.patch
-Patch53: backport-CVE-2022-47696.patch
-Patch54: backport-CVE-2021-46174.patch
-Patch55: backport-CVE-2023-1972.patch
-Patch56: backport-CVE-2022-48064.patch
-Patch57: backport-CVE-2022-4285.patch

 Provides: bundled(libiberty)

 Buildroot: %(mktemp -ud %{_tmppath}/%{name}-%{version}-%{release}-XXXXXX)

 BuildRequires: gcc, perl, sed, coreutils, dejagnu, zlib-devel, glibc-static, sharutils, bc, libstdc++-static
-BuildRequires: bison, m4, gcc-c++, gettext, flex, zlib-devel, texinfo >= 4.0, perl-podlators chrpath
-Requires(post): info coreutils chkconfig
-Requires(preun):info chkconfig
+BuildRequires: bison, m4, gcc-c++, gettext, flex, zlib-devel, texinfo >= 4.0, perl-podlators, chrpath
+Requires(post):  info coreutils chkconfig
+Requires(preun): info chkconfig

 %define _gnu %{nil}
 # The higher of these two numbers determines the default ld.
@ -164,12 +200,12 @@ touch */configure

 %build
 CARGS=
-case %{_target_platform} in i?86*|arm*|aarch64*|riscv64*)
+case %{_target_platform} in i?86*|arm*|aarch64*|riscv64*|loongarch64*|ppc64le*)
  CARGS="$CARGS --enable-64-bit-bfd"
  ;;
 esac

-case %{_target_platform} in x86_64*|i?86*|aarch64*|riscv64*)
+case %{_target_platform} in x86_64*|i?86*|aarch64*|riscv64*|loongarch64*|ppc64le*)
  CARGS="$CARGS --enable-targets=x86_64-pep --enable-relro=yes"
  ;;
 esac
@ -301,6 +337,60 @@ INPUT ( %{_libdir}/libopcodes.a -lbfd )
 EOF
 %endif

+%ifarch loongarch64
+tee %{buildroot}%{_libdir}/libbfd.so <<EOF
+/* GNU ld script */
+
+OUTPUT_FORMAT(elf64-loongarch)
+
+INPUT ( %{_libdir}/libbfd.a -liberty -lz -ldl )
+EOF
+
+tee %{buildroot}%{_libdir}/libopcodes.so <<EOF
+/* GNU ld script */
+
+OUTPUT_FORMAT(elf64-loongarch)
+
+INPUT ( %{_libdir}/libopcodes.a -lbfd )
+EOF
+%endif
+
+%ifarch sw_64
+tee %{buildroot}%{_libdir}/libbfd.so <<EOF
+/* GNU ld script */
+
+OUTPUT_FORMAT(elf64-sw_64)
+
+INPUT ( %{_libdir}/libbfd.a -liberty -lz -ldl )
+EOF
+
+tee %{buildroot}%{_libdir}/libopcodes.so <<EOF
+/* GNU ld script */
+
+OUTPUT_FORMAT(elf64-sw_64)
+
+INPUT ( %{_libdir}/libopcodes.a -lbfd )
+EOF
+%endif
+
+%ifarch ppc64le
+tee %{buildroot}%{_libdir}/libbfd.so <<EOF
+/* GNU ld script */
+
+OUTPUT_FORMAT(elf64-littleppc64le)
+
+INPUT ( %{_libdir}/libbfd.a -liberty -lz -ldl )
+EOF
+
+tee %{buildroot}%{_libdir}/libopcodes.so <<EOF
+/* GNU ld script */
+
+OUTPUT_FORMAT(elf64-littleppc64le)
+
+INPUT ( %{_libdir}/libopcodes.a -lbfd )
+EOF
+%endif
+
 rm -f %{buildroot}%{_infodir}/dir
 rm -rf %{buildroot}%{_prefix}/%{_target_platform}

@ -376,6 +466,24 @@ fi
 %{_infodir}/bfd*info*

 %changelog
+* Wed May 29 2024 yuzeyang <yuzeyang4@huawei.com> - 2.37-28
+- add l4 support
+
+* Thu Mar 21 2024 peng.zou <peng.zou@shingroup.cn> - 2.37-27
+- add ppc64le support
+
+* Fri Mar 08 2024 eastb233 <xiezhiheng@huawei.com> - 2.37-26
+- Support AArch64 SME
+
+* Mon Dec 25 2023 luguangyang <luguangyang@xfusion.com> - 2.37-25
+- fix CVE-2022-38533
+
+* Thu Sep 07 2023 yeqinglong <yeqinglong@kylinsec.com.cn> - 2.37-24
+- DESC:Add sw_64 support
+- DESC:Add LoongArch support
+- DESC:Fix LoongArch PLT entry generate bug
+- DESC:Add .equ support for LoongArch and fix some bugs
+
 * Tue Sep 05 2023 eastb233 <xiezhiheng@huawei.com> - 2.37-23
 - Delete post, preun, postun for help package

@ -415,16 +523,16 @@ fi
 * Sat Oct 08 2022 Chenxi Mao <chenxi.mao@suse.com> - 2.37-12
 - Fix Aarch64 EFI PE section address overlap issue.

-* Fri Sep 02 2022 Wei, Qiang <qiang.wei@suse.com> - 2.37-11
+* Thu Sep 08 2022 Wei, Qiang <qiang.wei@suse.com> - 2.37-11
 - Fix man page empty issue

-* Thu Sep 8 2022 yinyongkang <yinyongkang@kylinos.cn> - 2.37-10
+* Thu Sep 08 2022 yinyongkang <yinyongkang@kylinos.cn> - 2.37-10
 - Type:CVE
 - ID:CVE-2022-38126
 - SUG:NA
 - DESC:Fix CVE-2022-38126

-* Tue Aug 11 2022 dingguangya <dingguangya1@huawei.com> - 2.37-9
+* Thu Aug 11 2022 dingguangya <dingguangya1@huawei.com> - 2.37-9
 - Type:requirements
 - ID:NA
 - SUG:NA
--- a/sw_64-support-not-upstream-modified-files.patch
+++ b/sw_64-support-not-upstream-modified-files.patch
--- a/sw_64-support-not-upstream-new-files.patch
+++ b/sw_64-support-not-upstream-new-files.patch
Author	SHA1	Message	Date
openeuler-ci-bot	bfd875ebb7	!284 add l4 support From: @yzyssdd Reviewed-by: @li-yancheng, @huang-xiaoquan Signed-off-by: @li-yancheng	2024-05-29 13:20:13 +00:00
yzyssdd	4384c48b1d	add l4 support	2024-05-29 14:28:25 +08:00
openeuler-ci-bot	83e395e59b	!274 add ppc64le support From: @peng_zou Reviewed-by: @eastb233 Signed-off-by: @eastb233	2024-03-21 11:19:08 +00:00
邹鹏	67d9585cc5	add ppc64le support	2024-03-21 16:17:20 +08:00
openeuler-ci-bot	0b514da5db	!271 AArch64: Support SME instructions From: @eastb233 Reviewed-by: @huang-xiaoquan, @cf-zhao Signed-off-by: @cf-zhao	2024-03-20 01:07:52 +00:00
eastb233	af51a301bd	AArch64: Support SME instructions	2024-03-08 15:14:40 +08:00
openeuler-ci-bot	f4624feb64	!259 fix CVE-2022-38533 From: @lgylouis Reviewed-by: @eastb233 Signed-off-by: @eastb233	2024-01-03 07:39:08 +00:00
luguangyang	ecfd010cd2	[Backport]binutils:fix CVE-2022-38533 CVE:CVE-2022-38533 Reference:https://sourceware.org/git/?p=binutils-gdb.git;a=patch;h=ef186fe54aa6d281a3ff8a9528417e5cc614c797 Type:CVE reason:fix CVE-2022-38533	2023-12-25 16:11:45 +08:00
openeuler-ci-bot	57d46caffa	!244 add loongarch64 and sw_64 support From: @yeqinglong01 Reviewed-by: @eastb233 Signed-off-by: @eastb233	2023-10-09 03:19:50 +00:00
yeqinglong	d5ba1a2aea	add loongarch64 and sw_64 support	2023-09-22 10:50:23 +08:00